CISE Postdoctoral Program: Research in Computer Aided Design of VLSI Circuits with Emphasis on Deep Submicron Technology

CISE博士后项目：以深亚微米技术为重点的VLSI电路计算机辅助设计研究

• 批准号: 9625910
• 负责人: Ernest Kuh
• 金额: $ 2.09万
• 依托单位: University of California-Berkeley
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1996
• 资助国家: 美国
• 起止时间: 1996-03-15 至 1998-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9625910&HistoricalAwards=false
• 关键词: CISE; Postdoctoral; Program; Research; Computer

9625910 Kuh, Ernest S. University of California, Berkeley CISE Postdoctoral Program: Research in Computer Aided Design of VLSI Circuits with Emphasis on Deep Submicron Technology This award supports associate John P. Lillis. With the advent of deep submicron technology, the VLSI community is now faced with many new technical challenges which are currently inadequately addressed by the state of the art in Computer Aided Design for VLSI circuits. Because of the scaling of feature size in the submicron domain, performance of VLSI systems is now largely dominated by interconnect delay. Some powerful techniques for addressing this interconnect dominance are timing optimization by buffer insertion, wire sizing and performance driven routing. We propose that the time during the award period be used to further develop these techniques into a mature, cohesive set of tools. Among the research objectives of the proposals are (1) development of algorithms for routing and buffer insertion to address the problems of electromigration and crosstalk noise, (2) experimental evaluation of gate replication techniques for timing optimization and (3) integration of the optimization techniques at a higher level in the physical layout process which included circuit placement. All of these topics are of great practical importance in deep submicron systems of today and the future.

9625910 Kuh，Ernest S. 加州伯克利大学 CISE博士后流动站：深亚微米技术的VLSI电路计算机辅助设计研究 该奖项支持助理约翰·P·利利斯（John P. Lillis）。 随着深亚微米技术的出现，VLSI界现在面临着许多新的技术挑战，这些挑战目前在VLSI电路的计算机辅助设计中还没有得到充分的解决。 由于在亚微米领域的特征尺寸的缩放，VLSI系统的性能现在很大程度上由互连延迟决定。 解决这种互连优势的一些强大技术是通过缓冲器插入、导线尺寸和性能驱动的布线进行时序优化。 我们建议，在授予期间的时间被用来进一步发展这些技术成为一个成熟的，有凝聚力的工具集。 这些建议的研究目标包括 (1)开发用于布线和缓冲器插入的算法，以解决电迁移和串扰噪声的问题，（2）用于时序优化的栅极复制技术的实验评估，以及（3）在包括电路布局的物理布局过程中在更高级别上集成优化技术。 所有这些课题在深亚微米系统的今天和未来都具有重要的实际意义。