Research on Layout, Interconnection, and Testing

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This research covers VLSI physical design problems: macrocell- based custom chip layout, interconnection within and between VLSI chips, and design for testability. Layout problems are considered within a hierarchical automatic building-block layout system. The problems are on timing-driven layout and optimum layout of power and ground nets. The later problem is considered for the case of three metal layers. Theory and algorithms for interconnection problems are being pursued; and two specific problems are being solved. These are: three-dimensional module interconnect including estimates of length and space, and global and detailed routing. Also being considered are problems in routing methodology for long-wire dominated custom chips and routing for wafer-scale integration. Research at the interface between layout and testing is being addressed. In particular, validation of assumptions made for design for testability and reduction of hard-to-detect faults through layout are being investigated. Computational geometry is being used to understand the problem of designing repairable arrays.