Research on Layout, Interconnection, and Testing

布局、互连和测试研究

• 批准号: 8803711
• 负责人: Ernest Kuh
• 金额: $ 38.9万
• 依托单位: University of California-Berkeley
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1988
• 资助国家: 美国
• 起止时间: 1988-12-01 至 1992-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8803711&HistoricalAwards=false
• 关键词: Research; Layout; Interconnection; Testing

This research covers VLSI physical design problems: macrocell- based custom chip layout, interconnection within and between VLSI chips, and design for testability. Layout problems are considered within a hierarchical automatic building-block layout system. The problems are on timing-driven layout and optimum layout of power and ground nets. The later problem is considered for the case of three metal layers. Theory and algorithms for interconnection problems are being pursued; and two specific problems are being solved. These are: three-dimensional module interconnect including estimates of length and space, and global and detailed routing. Also being considered are problems in routing methodology for long-wire dominated custom chips and routing for wafer-scale integration. Research at the interface between layout and testing is being addressed. In particular, validation of assumptions made for design for testability and reduction of hard-to-detect faults through layout are being investigated. Computational geometry is being used to understand the problem of designing repairable arrays.

这项研究涵盖了VLSI物理设计问题：基于宏单元的定制芯片布局、VLSI芯片内部和芯片之间的互连以及可测试性设计。布局问题是在分层自动构建块布局系统中考虑的。这些问题是关于定时驱动的布局和电源和地网的优化布局。后一个问题被考虑为三层金属的情况。正在研究互联问题的理论和算法；正在解决两个具体问题。它们是：三维模块互连，包括长度和空间估计，以及全局和详细布线。此外，还在考虑长线主导的定制芯片的布线方法中的问题，以及晶片规模集成的布线问题。正在对布局和测试之间的接口进行研究。特别是，正在调查对可测试性设计的假设进行验证，并通过布局减少难以检测的故障。计算几何被用来理解设计可修复阵列的问题。