Research on Design Methodologies for High-Density, High- Performance, Wire-Dominated Chips and Multichip Modules

高密度、高性能、线控芯片和多芯片模块的设计方法研究

• 批准号: 9117328
• 负责人: Ernest Kuh
• 金额: $ 54.5万
• 依托单位: University of California-Berkeley
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1992
• 资助国家: 美国
• 起止时间: 1992-05-01 至 1996-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9117328&HistoricalAwards=false
• 关键词: Research; Design; Methodologies; Density; Performance

Kuh This a joint project with the UC at Berkeley (S. Kuh), UC at Santa Barbara (M. Marek-Sadowska) and UC at San Diego (C.-K. Cheng and T.C. Hu). Integrated circuit (IC) design is now dominated by wires which can no longer be considered as perfect conductors. The long term goal of this research is to find a new CAD methodology for designing high-performance large and dense circuits which have a large portion of the physical layout occupied by the wires. New algorithms with major emphasis on ability to handle efficiently very large problem instances are being developed. These include algorithms for the problem of extended floor-planning; such as, performance-driven partitioning, timing simulation including transmission lines, clock skew optimization, routing and compaction. Also being developed are algorithms to solve problems which span the boundaries of several of these classical problems and explore dependencies which were previously not studied. Much of this research is common to high performance design of both high-density chips and multichip modules.

KUH这是与伯克利分校（S. Kuh），圣塔芭芭拉（M. Marek-Sadowska）和圣地亚哥分校（C.-K。Cheng and T.C. Hu）的UC的联合项目。 现在，集成电路（IC）设计由不再被视为完美导体的电线主导。 这项研究的长期目标是找到一种新的CAD方法，用于设计高性能大而密集的电路，这些电路具有大部分电线所占据的物理布局。 正在开发具有有效处理非常大的问题实例能力的新算法。 这些包括用于扩展地板规划问题的算法；例如，性能驱动的分区，包括传输线，时钟偏差优化，路由和压实的时序模拟。 还开发了算法来解决跨越这些经典问题的边界的问题，并探索了以前未研究的依赖性。 这项研究的大部分是高密度芯片和多芯片模块的高性能设计常见的。