Research on Design Methodologies for High-Density, High- Performance, Wire-Dominated Chips and Multichip Modules

点击翻译按钮获取中文摘要

Kuh This a joint project with the UC at Berkeley (S. Kuh), UC at Santa Barbara (M. Marek-Sadowska) and UC at San Diego (C.-K. Cheng and T.C. Hu). Integrated circuit (IC) design is now dominated by wires which can no longer be considered as perfect conductors. The long term goal of this research is to find a new CAD methodology for designing high-performance large and dense circuits which have a large portion of the physical layout occupied by the wires. New algorithms with major emphasis on ability to handle efficiently very large problem instances are being developed. These include algorithms for the problem of extended floor-planning; such as, performance-driven partitioning, timing simulation including transmission lines, clock skew optimization, routing and compaction. Also being developed are algorithms to solve problems which span the boundaries of several of these classical problems and explore dependencies which were previously not studied. Much of this research is common to high performance design of both high-density chips and multichip modules.