Research in Circuit Layout

电路布局研究

• 批准号: 8506901
• 负责人: Ernest Kuh
• 金额: $ 28.13万
• 依托单位: University of California-Berkeley
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1985
• 资助国家: 美国
• 起止时间: 1985-07-01 至 1988-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8506901&HistoricalAwards=false
• 关键词: Research; Circuit; Layout

As the density of components on a VLSI chip continues to grow, the need to develop computer-aided tools for custom chips is crucial for the continued advance of VLSI technology. This research concentrates on custom chip layout, an area in which major breakthrough is expected in the next decade. The aim here is to develop theoretical knowledge, efficient algorithms, and experimental layout systems. The long-term plan is to develop a goal-oriented, hierarchical, building block system (an automatic custom layout system for placement and routing in VLSI design) for custom VLSI chips. Logical design, simulation, and physical layout are run in parallel to reduce design time and produce error-free layout. Hierarchical simulators are to be integrated with a hierarchical building block layout system. System flexibility will allow designer's intervention.

随着超大规模集成电路芯片上元件密度的持续增长， 开发用于定制芯片的计算机辅助工具对于 超大规模集成电路技术的不断进步。 本研究集中于 定制芯片布局，这是一个有望在 未来十年 这里的目的是发展理论知识， 高效的算法和实验布局系统。 长期 计划是开发一个以目标为导向的、分层次的积木式系统 (an用于超大规模集成电路布局和布线的自动定制布局系统 设计）的定制VLSI芯片。 逻辑设计、仿真和 物理布局并行运行以减少设计时间和生产 无错误的布局。 分层模拟器将与 分层构建块布局系统。 系统灵活性将 允许设计师介入。