Research in Circuit Layout

电路布局研究

• 批准号: 8506901
• 负责人: Ernest Kuh
• 金额: $ 28.13万
• 依托单位: University of California-Berkeley
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1985
• 资助国家: 美国
• 起止时间: 1985-07-01 至 1988-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8506901&HistoricalAwards=false
• 关键词: Research; Circuit; Layout

As the density of components on a VLSI chip continues to grow, the need to develop computer-aided tools for custom chips is crucial for the continued advance of VLSI technology. This research concentrates on custom chip layout, an area in which major breakthrough is expected in the next decade. The aim here is to develop theoretical knowledge, efficient algorithms, and experimental layout systems. The long-term plan is to develop a goal-oriented, hierarchical, building block system (an automatic custom layout system for placement and routing in VLSI design) for custom VLSI chips. Logical design, simulation, and physical layout are run in parallel to reduce design time and produce error-free layout. Hierarchical simulators are to be integrated with a hierarchical building block layout system. System flexibility will allow designer's intervention.

随着VLSI芯片上组件的密度不断增长，开发用于定制芯片的计算机辅助工具的需求对于继续前进的VLSI技术至关重要。 这项研究集中在定制的芯片布局上，这是预计未来十年的重大突破的领域。 这里的目的是开发理论知识，有效的算法和实验布局系统。 长期计划是为自定义VLSI芯片开发面向目标的，层次，构建块系统（用于VLSI设计中的自动定制布局系统）。 逻辑设计，仿真和物理布局并行运行，以减少设计时间并产生无错误的布局。 分层模拟器应与层次结构块布局系统集成。 系统灵活性将允许设计师的干预。