Reconfigurable Architectures with Shift Switching for Novel Parallel Arithmetic Schemes

本研究将探讨一种新的VLSI算术设计方法，使用可重构架构与移位切换，旨在实现一种创新的设计方法，这可能会导致大幅改善的速度和面积的几个算术设备，包括并行计数器，并行压缩器，并行乘法器，预充电CMOS加法器/比较器，前缀并行计数器，以及基本功能评估。 所提出的技术将采用增强的可重构总线，即，总线包含移位开关，缓冲器正确插入。它具有以下新特点。 首先，当指定的数字信号通过移位开关总线传播时，可以直接执行所需的模运算，这简化了这种基本算术计算的传统模型。第二，在通过每个移位开关之后，状态信号以两种相互反相的形式（n和p）交替地反相，这使晶体管的负载最小化，并使电路的速度最大化。研究将集中在重要的算术运算的增强可重构总线为基础的VLSI方案的发展。 目标是调查：1。移位切换并行压缩器和条件压缩器; 2.有效的部分乘积约简方案; 3.专用阵列处理器，用于实现一些最优算术算法; 4.各种移位开关并行计数器方案及其应用; 5.预充电CMOS多米诺逻辑移位开关及其在运算器件和异步运算器件设计中的应用。

This research will investigate a novel VLSI arithmetic design approach using reconfigurable architectures with shift switching, aimed at achieving an innovative design methodology which could lead to a substantial improvement on both speeds and areas for several arithmetic devices including parallel counters, parallel compressors, parallel multipliers, precharged CMOS adders/comparators, prefix parallel counters, as well as elementary function evaluations. The proposed technique will employ enhanced reconfigurable buses, i.e., buses containing shift switches with buffers properly inserted. It possesses the following new features. First, when specified digital signals are propagating through shift switching buses, the desired modulo operations can be performed directly, which simplifies the traditional model of this basic arithmetic computation. Second, after passing through each shift switch, the state signals are inverted alternatively in two mutually inverted forms (n and p), which minimizes the load of transistors and maximizes the speed of circuits. The research will focus on the development of enhanced reconfigurable bus-based VLSI schemes for important arithmetic operations. The goals are to investigate: 1. shift switching parallel compressors and conditional compressors; 2. efficient partial product reduction schemes; 3. application-specific array processors for realization of some optimal arithmetic algorithms; 4. various shift switching parallel counter schemes and their applications; 5. shift switching with precharge CMOS domino logic and its applications in designing arithmetic devices and asynchronous arithmetic devices.