Reconfigurable Architectures with Shift Switching for Novel Parallel Arithmetic Schemes

用于新型并行算术方案的具有移位切换的可重构架构

• 批准号: 9630870
• 负责人: Rong Lin
• 金额: $ 11.04万
• 依托单位: SUNY College at Geneseo
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1996
• 资助国家: 美国
• 起止时间: 1996-08-01 至 2000-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9630870&HistoricalAwards=false
• 关键词: Reconfigurable; Architectures; Shift; Switching; Novel

This research will investigate a novel VLSI arithmetic design approach using reconfigurable architectures with shift switching, aimed at achieving an innovative design methodology which could lead to a substantial improvement on both speeds and areas for several arithmetic devices including parallel counters, parallel compressors, parallel multipliers, precharged CMOS adders/comparators, prefix parallel counters, as well as elementary function evaluations. The proposed technique will employ enhanced reconfigurable buses, i.e., buses containing shift switches with buffers properly inserted. It possesses the following new features. First, when specified digital signals are propagating through shift switching buses, the desired modulo operations can be performed directly, which simplifies the traditional model of this basic arithmetic computation. Second, after passing through each shift switch, the state signals are inverted alternatively in two mutually inverted forms (n and p), which minimizes the load of transistors and maximizes the speed of circuits. The research will focus on the development of enhanced reconfigurable bus-based VLSI schemes for important arithmetic operations. The goals are to investigate: 1. shift switching parallel compressors and conditional compressors; 2. efficient partial product reduction schemes; 3. application-specific array processors for realization of some optimal arithmetic algorithms; 4. various shift switching parallel counter schemes and their applications; 5. shift switching with precharge CMOS domino logic and its applications in designing arithmetic devices and asynchronous arithmetic devices.

本研究将探讨一种使用移位开关可重构架构的VLSI算术设计方法，旨在实现一种创新的设计方法，该方法可以在并行计数器、并行压缩器、并行乘法器、预充电的CMOS加法器/比较器、前缀并行计数器以及基本功能评估等几种算术器件的速度和面积上都有实质性的提高。所提出的技术将采用增强的可重新配置的总线，即，包含适当插入了缓冲器的移位开关的总线。它具有以下新功能。首先，当指定的数字信号通过移位开关总线传输时，可以直接执行所需的模运算，这简化了这种基本算术计算的传统模型。其次，经过每个移位开关后，状态信号交替地以两种相互反转的形式(n和p)进行反转，从而最小化晶体管的负载，最大化电路的速度。这项研究将集中于开发用于重要算术运算的增强型可重构总线VLSI方案。研究的目标是：1.移位开关并行压缩器和条件压缩器；2.有效的部分积缩减方案；3.用于实现一些优化算术算法的专用阵列处理器；4.各种移位开关并行计数器方案及其应用；5.带预充电的CMOS多米诺逻辑的移位开关及其在算术器件和异步算术器件设计中的应用。