CAREER: Building Scalable and Reliable Composable Computer Architectures

在后摩尔时代，计算平台变得更加多样化和异构化。随着封装和互连技术的发展，多个计算和存储组件被集成到单个处理器封装中。高带宽和相干互连使多个加速器和存储组件在一个平台上一起实现服务器规模的计算能力。尽管这种新的计算平台范例为特定领域的计算提供了更优的处理器设计，但其可伸缩性尚不清楚。芯片内和芯片间组件之间的快速互连不一定会导致线性加速，除非通信被仔细处理。该项目旨在通过可扩展的架构级解决方案跟上后摩尔时代摩尔定律的性能预测。由于图形处理单元（GPU）对于加速大数据工作负载越来越重要，本项目将专注于构建高度可扩展和可靠的GPU平台，该平台可以随着GPU芯片模块和存储设备的扩展而实现几乎线性的加速。提出的研究工具和虚拟存储系统将推进最先进的架构，在gpu内部和内部芯片组件之间具有连贯和可扩展的通信。所呈现的架构设计将能够加速新兴的大数据工作负载，而无需访问昂贵的云或数据中心超级计算机。研究结果将被纳入新的和现有的本科和研究生课程以及K-12外展计划。本项目旨在解决以下研究问题：1)如何管理所有集成的计算和存储组件以有效地通信？传统的虚拟内存系统能处理大量的地址转换吗？2)如何在多级非统一内存访问（NUMA）架构上实现可扩展和可持续的性能？是否可以强制执行一致的数据访问延迟？这个项目通过两个技术重点来回答这些问题。第一个重点是设计研究工具，使可扩展和异构平台的设计探索成为可能。然后，将构建高效的虚拟内存系统和页面映射算法。与现有的解决方案不同，本项目中提出的方法将利用独特的GPU执行模型，同时实现GPU内部和GPU之间的一致通信。第二个重点将探索在具有分解存储器的目标多gpu系统上执行可持续性能的方法。与传统系统相比，这些新平台面临更深层次NUMA的新挑战，因为单个计算和内存组件可以通过多层可扩展交换机集成。这种推力将设计有效的内存管理和预取算法，它们一起强制数据在1-2 NUMA距离内准备好。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

In the post-Moore era, computing platforms have become more diverse and heterogeneous. With the evolution of packaging and interconnect technology, multiple computing and memory components are integrated into a single processor package. The high-bandwidth and coherent interconnects enable multiple accelerators and memory components on a platform together achieve server scale computing power. Though this new paradigm of computing platforms enables more optimal processor designs for domain-specific computing, the scalability is unclear. The fast interconnects between intra- and inter-chip components do not necessarily lead to linear speedup unless the communications are carefully handled. This project aims to keep up with performance projection of Moore’s law in post-Moore era with scalable architecture-level solutions. As graphics processing units (GPUs) are increasingly important for accelerating big data workloads, this project will focus on architecting highly scalable and reliable GPU platforms that can achieve almost linear speedup with the scaling of GPU chiplet modules and memory devices. The presented research tools and virtual memory systems will advance the state-of-the-art architectures with coherent and scalable communications among the intra- and inter-GPU chiplet components. The presented architecture design will be able to accelerate emerging big-data workloads without needing to access expensive cloud or data center supercomputers. The research findings will be incorporated into new and existing undergraduate and graduate courses as well as K-12 outreach programs.This project aims to address the following research questions: 1) How to manage all the integrated computing and memory components to communicate efficiently? Can the conventional virtual memory system handle large volumes of address translations? 2) How to achieve scalable and sustainable performance over multi-level non-uniform memory access (NUMA) architectures? Can consistent data access latency be enforced? This project answers these questions through two technical thrusts. The first thrust will design research tools that enable design explorations of scalable and heterogeneous platforms. Then, efficient virtual memory systems and page mapping algorithms will be architected. Unlike existing solutions, the methods presented in this project will exploit the unique GPU execution model while enabling coherent communication among intra- and inter-GPU packages. The second thrust will explore methods to enforce sustainable performance on the target multi-GPU systems having disaggregated memories. These new platforms have emerging challenges of deeper NUMA levels than conventional systems because individual computing and memory components can be integrated through multiple levels of extensible switches. This thrust will design efficient memory management and prefetch algorithms, which together enforce data to be ready within 1-2 NUMA distances.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.