VLSI Arithmetic Logic Schemes and Low-Power High-Performance Circuits for Parallel and Reconfigurable Computations

用于并行和可重构计算的 VLSI 算术逻辑方案和低功耗高性能电路

• 批准号: 0073469
• 负责人: Rong Lin
• 金额: $ 13.53万
• 依托单位: SUNY College at Geneseo
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-07-01 至 2004-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0073469&HistoricalAwards=false
• 关键词: VLSI; Arithmetic; Logic; Schemes; Low

Proposal: CCR 0073469Title: New VLSI Arithmetic Logic Schemes and Low-Power High-Performance CircuitsFor Parallel and Reconfigurable ComputationsPI: Rong LinABSTRACTThis research investigates several basic parallel and reconfigurable arithmetic and elementary functional unit designs, architectures and algorithms. Recently developed non-binary VLSI shift switch logic schemes and low-power high-performance circuits are used for the study. A set of application specific processors, using the novel logic and the building-block circuits, has demonstrated superiority in VLSI design, which includes high-speed large-size array multipliers, reconfigurable inner product processors and reconfigurable matrix multipliers. Development of a dynamically reconfigurable platform for all of these computations is a major target of this project. The new logic schemes primarily employ shift switch parallel counter units as logic operators, and 4-bit digital signals, representing values ranging from 0 to 3, as logic operands, where only 2-out-of-4 signal bits are subject to value-change at any logic stage in the worst case. This is used to simplify the circuit designs and to reduce the power-dissipation. The main focus of this research is to further explore the properties and advantages of the logic schemes and circuits, and to develop superior applications for parallel and reconfigurable computations. A significant impact on the next generation of microprocessors and SOC designs is expected.

提案：本文研究了几种基本的并行和可重构运算和基本功能单元的设计、结构和算法。最近开发的非二进制VLSI移位开关逻辑方案和低功耗高性能电路用于研究。一组应用专用处理器，使用新的逻辑和积木式电路，已显示出优越的超大规模集成电路设计，其中包括高速大规模阵列乘法器，可重构内积处理器和可重构矩阵乘法器。为所有这些计算开发一个动态可重构的平台是这个项目的主要目标。新的逻辑方案主要采用移位开关并行计数器单元作为逻辑运算器，并采用4位数字信号作为逻辑操作数，表示范围从0到3的值，其中在最坏情况下，在任何逻辑级只有4个信号位中的2个发生值变化。这是用来简化电路设计和降低功耗。本研究的主要目的是进一步探讨这些逻辑架构与电路的特性与优势，并开发出并行与可重构计算的上级应用。预计将对下一代微处理器和SOC设计产生重大影响。