SBIR Phase II: In-Line Process Monitoring & Control for Poly-Silicon Formation Inside Cluster Tools

* 9631216所罗门 这个小企业创新研究第二阶段项目将开发傅里叶变换红外（FT-IR）仪器，用于在线监测和控制集群工具内的多晶硅和电介质制造过程。 本文提出了一种用傅立叶变换红外光谱法测定多晶硅和介质膜厚度、掺杂多晶硅膜的自由载流子浓度和散射率的方法。 该技术适用于多层和图案化样品，并且可以在晶片处于群集工具的冷却室中时实时执行测量和分析。 在德州仪器的群集工具上进行的第一阶段现场测试建立了测量掺杂和未掺杂多晶硅膜、相对厚（250 nm）的场氧化物、薄（10 nm）的栅氧化物和图案化晶片的能力。 将作出协作努力，以便：1）在群集工具上开发测试精细的在线FT-IR工艺监测器，2）开发用于分析毯式和图案化晶片上的多层多晶硅/介电膜的稳健自动化软件，3）开发用于测量介电和多晶硅性质的均匀性的高速晶片映射系统，以及4）开发工艺监测，优化和控制软件以及分析方法。 该项目将产生坚固耐用的多应用仪器，用于在线监测和控制在集群工具中进行的各种制造过程。 该项目可以提高集成电路（IC）的生产良率，消除因未检测到的不合格晶圆而报废的批次，减少人力需求，并缩短启动和高良率生产之间的时间。 晶圆测绘工具也将是有用的许多其他集成电路制造工艺，如外延和离子注入的质量控制。 ***

*** 9631216 Solomon This Small Business Innovation Research Phase II Project will develop Fourier transform infrared (FT-IR) instrumentation for in-line monitoring and control of poly-silicon and dielectric fabrications processes within a cluster tool.. An FT-IR based method to determine polysilicon and dielectric film thicknesses, and free carrier concentrations and scattering rates of doped poly films has been developed. The technique is adaptable to multilayered and patterned samples, and the measurement and analysis can be performed in real-time, while the wafer is in the cooldown chamber of the cluster tool. Field tests in Phase I on a cluster tool at Texas Instruments established the capability to measure doped and undoped poly films, relatively thich ((250 nm) field oxides, thin ((10nm) gate oxides, and patterned wafers. A collaborative effort will be made to: 1) develop test a refined in-line FT-IR process monitor on the cluster tool, 2) Develop robust automated software for analysis of multilayered poly/dielectric films on blanket and patterned wafers, 3) Develop a high speed wafer mapping system for measuring uniformity of dielectric and poly properties, and 4) Develop process monitoring, optimization and control software and analysis methodology. This project will result in rugged multi-applications instrumentation for in-line monitoring and control of a wide range of fabrication processes performed in a cluster tool. This project can increase integrated circuits (IC) production yield, eliminate scrapped batches due to undetected out-of-spec wafers, reduce manpower requirements, and reduce the time between start-up and high yield production. The wafer mapping tool will also be useful for quality control of many other IC fabrication processes such as epi and ion implantation. ***