CAREER: Research in Low Noise Integrated Circuit Design for Telecommunication Systems

本研究的目的是探讨一类低噪声集成振荡器的设计方法在电信，高速微处理器和过采样数据转换的应用领域的扩展。 与本研究相关的教学计划的目标是模拟微电子实验室成为一个完整的资源，教育本科生和研究生在完整的集成电路设计过程。 该项目将改进电信系统的模拟和混合信号集成电路的设计，其中系统级性能最终受到基本电路级考虑的限制。 任何集成通信系统中的关键部件是为数据传输和检测过程提供时间/频率参考的振荡器。 环形振荡器的种类繁多，为集成振荡器设计提供了许多优势，但直到最近，还没有可用于设计所需噪声性能水平的程序。 该项目基于一种新的环形振荡器设计方法，该方法已被证明在双极IC工艺中成功地实现了高达155 MHz的频率。 目标是将低抖动振荡器设计技术扩展和拓宽到GHz范围内的更高速度，降低3.3V及以下的电源电压，以及包括CMOS在内的其他制造技术。

The goal of this research is to investigate extensions of a design methodology for a class of low noise integrated oscillators in the applications areas of telecommunications, high speed microprocessors, and oversampled data conversion. The goal of the teaching plan associated with this research is for the Analog Microelectronics Laboratory to become an integral resource for educating both undergraduates and graduate students in the complete integrated circuit design process. This project will improve the design of analog and mixed signal integrated circuits for telecommunication systems in which system-level performance is ultimately limited by fundamental circuit-level considerations. A critical component in any integrated communication system is an oscillatory that provides a time/frequency reference for the data transmission and detection process. The broad class of ring oscillators offer many advantages for integrated oscillator design, but until recently there were no procedures available to design for a desired level of noise performance. This project is based on a new design methodology for ring oscillators that has been proven successful to the frequencies up to 155 MHz in a bipolar IC process. The goal is to extend and broaden the low jitter oscillator design techniques to higher speed in the GHz range, reduced supply voltage of 3.3V and below, and other fabrication technologies including CMOS.