Mixed Signal Techniques for Analog-to-Digital Converter Design with Sub-Picosecond Time-Domain Performance in Nanometer CMOS

纳米级CMOS亚皮秒时域性能模数转换器设计的混合信号技术在许多快速发展的混合信号应用领域，如超宽带无线数据标准、有线串行数据传输和高密度磁盘驱动器，都需要低成本高性能模数转换器。 为了满足这些领域的需求，所提出的工作的目标是设计，测试和验证低成本，高速，高能效的模数转换器的采样率从3到40 GSps和5-8位的分辨率。 所提出的方法的新颖方面解决了模数转换器校准和采样时钟定时精度方面的困难。 校准是通过扩展的主要研究者专门针对纳米级数字集成电路技术的限制开发的背景数字校正技术来解决的。这种校正技术已经被主要研究者（和许多其他人）广泛地研究，作为在多种更高分辨率（12-16位）、更低速度（1-100 MSps）架构（包括循环、连续近似、流水线、时间交织和过采样）中有前途的方法。 在拟议的工作中，该技术将首次应用于数字背景校准的闪光灯模数转换器的速度为1 GSps和更高。在这些转换速率下工作要求采样时钟时序误差（抖动）小于1皮秒。 为了解决样本时钟定时问题，主要研究者？的先前工作与振荡器噪声的基本限制将被利用，使低抖动高速片内时钟产生从一个中等成本，低频率，商业现成的频率基准。 将这些技术结合起来，将产生一种低成本、高速模数转换能力，可满足各种新兴混合信号应用的需求。 特别是，在低功耗至关重要时，例如在移动的和无限制的应用中，以节能方式实现这种能力将允许系统功能的持续改进。 除了技术进步外，该项目还将通过支持一个博士学位来促进扩大教育的目标。学生进行了大量的研究工作。 在招聘该职位时，将尽一切努力从任职人数不足的群体中确定一个人。研究成果将被整合到研究生和本科生的课堂和项目材料中;这已被证明可以提高学生对混合信号集成电路设计领域的参与度和兴趣。 最后，将通过开放获取设计信息的方式，向更广泛的技术界提供各种详细程度的研究材料。

MIXED SIGNAL TECHNIQUES FOR ANALOG-TO-DIGITAL CONVERTER DESIGN WITH SUB-PICOSECOND TIME-DOMAIN PERFORMANCE IN NANOMETER CMOSPROJECT ABSTRACTIntellectual Merit Low-cost high-performance analog-to-digital converters are required in many rapidly growing mixed-signal application areas such as ultrawideband wireless data standards, wireline serial data transmission, and high-density disk drives. To address needs in these areas, the objective of the proposed work is the design, test, and verification of low cost, high speed, energy efficient analog-to-digital converters operating at sample rates from 3 to 40 GSps and resolutions of 5-8 bits. Novel aspects of the proposed approach address difficulties in the area of analog-to-digital converter calibration and precision of sample clock timing. Calibration is addressed by extending a background digital correction technique developed by the principal investigator specifically tailored to the constraints of nanometer-scale digital integrated circuit technology. This correction technique has been extensively investigated by the principal investigator (and many others) as a promising approach in a diversity of higher resolution (12-16 bits), lower speed (1-100 MSps) architectures including cyclic, successive approx¬imation, pipeline, time-interleaved, and oversampling. In the proposed work, the technique will be applied for the first time to digital background calibration of flash analog-to-digital converters operating at speeds of 1 GSps and higher. Operating at these conversion rates requires that sample clock timing errors (jitter) be less than 1 picosecond. To address sample clock timing issues, the principal investigator?s previous work with fundamental limits on oscillator noise will be leveraged to enable low jitter high speed on-chip clock generation from a moderate cost, low frequency, commercial-off-the-shelf frequency reference. Broader Impacts Combining these techniques will result in a low-cost, high speed analog-to-digital conversion capability required for a wide range of emerging mixed-signal applications. In particular, achieving this capability in an energy-efficient manner will allow continued improvement in system functionality when low power consumption is critical; for example, in mobile and untethered applications. In addition to technical advances, the project will also contribute to the goal of expanding education by supporting a Ph.D. student to perform much of the research work. Every effort will be made to identify an individual from an underrepresented group when recruiting for this position. Research results will be integrated into classroom and project materials at both the graduate and undergraduate levels; this has proven to increase student engagement and interest in the field of mixed signal integrated circuit design. Finally, research materials at all levels of detail will be made available to the wider technical community through open access to design information.