Mixed Signal Techniques for Analog-to-Digital Converter Design with Sub-Picosecond Time-Domain Performance in Nanometer CMOS

摘要智能优点在超宽带无线数据标准、有线串行数据传输和高密度磁盘驱动器等快速发展的混合信号应用领域，需要低成本、高性能的模数转换器。为了满足这些领域的需求，拟议工作的目标是设计，测试和验证低成本，高速，节能的模数转换器，其采样率为3至40 GSps，分辨率为5-8位。该方法的新颖之处在于解决了模数转换器校准和采样时钟定时精度方面的困难。校准是通过扩展一个背景数字校正技术开发的主要研究者专门针对纳米尺度的数字集成电路技术的限制。这种校正技术已经被首席研究员（和许多其他人）广泛研究，作为一种有前途的方法，适用于各种高分辨率（12-16位）、低速度（1-100 MSps）架构，包括循环、连续近似、管道、时间交错和过采样。在提出的工作中，该技术将首次应用于以1 GSps或更高速度工作的闪存模数转换器的数字背景校准。在这些转换速率下工作要求采样时钟定时误差（抖动）小于1皮秒。解决样品时钟计时问题，首席研究员？S先前对振荡器噪声进行基本限制的工作将利用中等成本，低频，商用现成的频率基准来实现低抖动的高速片上时钟生成。更广泛的影响结合这些技术将产生低成本，高速模数转换能力，需要广泛的新兴混合信号应用。特别是，在低功耗至关重要的情况下，以节能的方式实现这一功能将允许系统功能的持续改进；例如，在移动和非绑定应用程序中。除了技术进步之外，该项目还将通过支持博士生进行大部分研究工作来促进扩大教育的目标。在招聘这个职位时，我们将尽一切努力从代表性不足的群体中挑选一个人。研究成果将纳入研究生和本科生的课堂和项目材料；事实证明，这增加了学生对混合信号集成电路设计领域的参与和兴趣。最后，通过对设计信息的开放获取，将所有详细程度的研究材料提供给更广泛的技术界。

MIXED SIGNAL TECHNIQUES FOR ANALOG-TO-DIGITAL CONVERTER DESIGN WITH SUB-PICOSECOND TIME-DOMAIN PERFORMANCE IN NANOMETER CMOSPROJECT ABSTRACTIntellectual Merit Low-cost high-performance analog-to-digital converters are required in many rapidly growing mixed-signal application areas such as ultrawideband wireless data standards, wireline serial data transmission, and high-density disk drives. To address needs in these areas, the objective of the proposed work is the design, test, and verification of low cost, high speed, energy efficient analog-to-digital converters operating at sample rates from 3 to 40 GSps and resolutions of 5-8 bits. Novel aspects of the proposed approach address difficulties in the area of analog-to-digital converter calibration and precision of sample clock timing. Calibration is addressed by extending a background digital correction technique developed by the principal investigator specifically tailored to the constraints of nanometer-scale digital integrated circuit technology. This correction technique has been extensively investigated by the principal investigator (and many others) as a promising approach in a diversity of higher resolution (12-16 bits), lower speed (1-100 MSps) architectures including cyclic, successive approx¬imation, pipeline, time-interleaved, and oversampling. In the proposed work, the technique will be applied for the first time to digital background calibration of flash analog-to-digital converters operating at speeds of 1 GSps and higher. Operating at these conversion rates requires that sample clock timing errors (jitter) be less than 1 picosecond. To address sample clock timing issues, the principal investigator?s previous work with fundamental limits on oscillator noise will be leveraged to enable low jitter high speed on-chip clock generation from a moderate cost, low frequency, commercial-off-the-shelf frequency reference. Broader Impacts Combining these techniques will result in a low-cost, high speed analog-to-digital conversion capability required for a wide range of emerging mixed-signal applications. In particular, achieving this capability in an energy-efficient manner will allow continued improvement in system functionality when low power consumption is critical; for example, in mobile and untethered applications. In addition to technical advances, the project will also contribute to the goal of expanding education by supporting a Ph.D. student to perform much of the research work. Every effort will be made to identify an individual from an underrepresented group when recruiting for this position. Research results will be integrated into classroom and project materials at both the graduate and undergraduate levels; this has proven to increase student engagement and interest in the field of mixed signal integrated circuit design. Finally, research materials at all levels of detail will be made available to the wider technical community through open access to design information.