Reducing Cost and Improving Energy Efficiency in Portable Sensor Electronics for Healthcare, Communication, and Security

每当必须将来自物理世界的信号转换成微处理器或计算机能够理解的形式时，就需要模数转换器(ADC)。应用实例包括用于辅助技术的植入式生物医学设备、用于非束缚医疗监测的自主供电传感器、用于智能手机的加速计和其他传感器，以及用于汽车和安全应用的化学传感器。在大多数这样的系统中，可用能量受到电池功率或清除的能量限制的严重限制。高精度ADC的另一个困难是对校准的要求，这增加了制造和运营成本。这项工作的目标是利用数字集成电路制造技术的进步，提供适用于各种快速发展的技术领域的高能效自校准ADC。拟议的高能效方法将使ADC的功耗降低至少10倍，支持新的系统架构和功能，并延长现有系统的电池寿命。自校准可以减少制造和运营费用，这对于提供最终用户预期的成本改善至关重要。在拟议的工作中，原型集成电路将在纳米级(28纳米)集成电路工艺中设计、制造和测试。(设计和验证过程将使用最先进的设计软件和调查员研究实验室提供的测试设备进行。这本身就是一次宝贵的劳动力教育经验，因为学生研究人员将执行与工业中使用的非常相似的设计过程。)集成电路技术向纳米尺寸的扩展使数字电源效率大幅提高，电源电压更低，逻辑功能的功耗也更低。然而，大多数传统上流行的ADC结构并不能很好地适应较低的电源电压环境，对于其他结构的研究正在进行中。数字速度的提高带来的时间分辨率的提高自然会推动设计朝着时域结构发展，这种结构已经显示出希望，但还不能同时提供高精度和高能效。拟议的活动将首席研究人员先前在精确时基电路方面的工作与数字校准的ADC技术相结合。由此产生的研究将使一类超低功耗、高效率的ADC架构适用于需要低成本、高精度和能效的各种新兴应用。

Analog-to-digital converters (ADCs) are required whenever a signal from the physical world must be translated into a form that can be understood by a microprocessor or computer. Example applications include implanted biomedical devices for assistive technology, autonomously powered sensors for untethered health care monitoring, accelerometers and other sensors used in smartphones, and chemical sensors used in automotive and security applications. In most of these systems, available energy is severely constrained by battery power or scavenged energy limits. An additional difficulty for high precision ADCs is the requirement for calibration, which increases both manufacturing and operating costs. The goal of this work is to leverage advancement in digital integrated circuit manufacturing technology to provide a class of energy-efficient self-calibrating ADCs applicable across a wide range of rapidly growing technology areas. The proposed energy efficient approach would reduce ADC power consumption by at least a factor of 10, enabling new system architectures and capabilities, as well as extended battery life in existing systems. Self calibration allows reduction in manufacturing and operating expense, critical to providing the cost improvement end users expect. In the proposed work, prototype integrated circuits will be designed, fabricated, and tested in a nanoscale (28nanometers) integrated circuit process. (The design and verification process will be carried out using state-of-the-art design software and test equipment available in the investigator's research lab. This in itself is a valuable workforce education experience, as the student researcher will be carrying out a design process very similar to that used in industry.) Scaling of integrated circuit technology to nanometer dimensions has enabled dramatic improvement in digital power efficiency, with lower power supply voltage and decreased power consumption for logic functions. However, most traditionally prevalent ADC architectures are not well suited to the lower supply voltage environment, and investigation is ongoing for other architectures. The improvement in time resolution enabled by increased digital speeds naturally drives design toward time-domain architectures, which have shown promise but have not yet been able to provide both high accuracy and high energy efficiency. The proposed activity combines the principal investigator's previous work on precise time-based circuitry with digitally calibrated ADC techniques. The resulting research will enable a class of ultra-low-power, efficient ADC architectures suitable for a wide range of emerging applications requiring low cost, high accuracy, and energy efficiency.