Background Calibration Technique for High-Resolution Analog to Digital Converters in Submicron CMOS

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McNeill 0523996This integrative systems proposal focuses on development of a new class of self-calibrating analog-to-digital converters (ADCs). The new "Split ADC" architecture enables integration of high resolution; self-calibrating ADCs at low cost with advanced digital CMOS integrated circuits (ICs). This capability fills a critical need in a wide range of emerging mixed signal application areas, including integrated sensors for biomedical and homeland security applications. In terms of intellectual merit, the new "Split ADC" architecture represents a genuine creative design breakthrough in response to the specific constraints of advanced digital CMOS processing technology. The PIs previous work in developing the "split ADC" architecture has been proven by successful fabrication and test of a 16bit, 1MSample/s, cyclic ADC. This is an indication of both the validity of the concept to be extended and the PI's ability to successfully complete the proposed work.Broader impacts: The successful completion of the work described in this proposal will extend development of this new class of self-calibrating ADCs to the important application area of interleaved ADCs. The project will also contribute to the goal of expanding education by supporting a Ph.D. student to perform the bulk of the research work. Results of this research will be used as a module in a graduate-level circuit design course. Additionally, the PI will involve undergraduate students in this research effort.