Unified Algorithms and Architectures for Low-Power Wireless Video

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The demand for real-time image and video communications places unprecedented demands on power and data-rate-limited communication links. Present day communication systems are primarily designed for data communications at a fixed rate and are poorly matched to video data, which is more tolerant of errors and is characterized by fluctuating rates. The quality of wireless channels can also vary greatly, and the video coding and transmission should be adapted to these changing conditions. Existing hardware implementations are equally inflexible, being designed independently for pre-specified conditions and a fixed power consumption. The match between current video compressors, wireless modems, and their hardware is thus often very poor. This research addresses the joint design of video communication components to maximize the overall system design of video communication components to maximize the overall system performance. While achieving unprecedented performance in low-power image and video transmission over wireless channels, this research also develops a powerful and general new methodology for directly coupling chip design with signal processing algorithms and overall system optimization. The research obtains dramatic improvements in end-to-end video transport over wireless communication links through adaptive, joint optimization of source coding, channel coding, and VLSI computation. Instead of selecting fixed operating points for the source coder, channel coder, and the VLSI hardware, dynamically adjustable coders and hardware supporting a variety of operating points is being developed. Specific research tasks to achieve this overall system goal include: (1) the development of rate-distortion-optimized coders based on multi-resolution data structures and tolerance to bit errors; (2) multi- resolution channel coding methods supporting variable rate-vs.-quality data transmission for multiple channels; (3) real-time reconfigurable hardware via Dynamic Algorit hm Transformations (DAT) to achieve low-power operation at various operating points, and, (4) joint optimization of the above three components subject to overall system power constraints.