Applications and Tools for Configurable Computing in Sequential and Parallel Computers

可配置计算可以为每个应用定制计算环境的硬件。 最近，一些基于现场可编程门阵列的可配置机器已经显示出比更传统的处理器显著的性能改进。 然而，这种性能的代价是细致和耗时的算法映射。 这项研究包括两个项目，试图降低进入可配置计算的成本。 在单处理器领域，性能监控和编译技术正在研究中的系统，集成可配置硬件与传统的处理器。 利用SUIF编译器技术，该项目致力于识别和优化代码段，这些代码段既耗时又可使用可配置硬件实现。 这些代码包括面向流的数据处理、不规则逻辑运算和短整数运算。 在多处理器领域，FPGA正被用于实现特定于应用的高速缓存一致性协议处理器. 这项工作的主要贡献将是研究特定于应用程序的软件，可配置的硬件和自定义硬件的性能权衡。 这些可能会导致特定于应用程序的协议的扩展的好处。

Configurable computing can customize the hardware of a computing environment for each application. Recently some configurable machines based on field- programmable gate arrays have shown significant performance improvement over more traditional processors. However, this performance has come at the cost of meticulous and time-consuming algorithm mapping. This research consists of two projects that attempt to lower the cost of entry to configurable computing. In the uniprocessor domain, performance monitoring and compilation techniques are under investigation for systems that integrate configurable hardware with traditional processors. Drawing on SUIF compiler technology, this project is working toward identification and optimization of code sections that are both time consuming and implementable using configurable hardware. Such code includes stream-oriented data processing, irregular logic operations, and short integer arithmetic. In the multiprocessor domain, FPGAs are being used to implement application- specific cache coherence protocol processors. The key contribution of this work will be studying the performance tradeoffs of application-specific software, configurable hardware, and custom hardware. These may lead to expanded benefits for application-specific protocols.