EHS: Adaptive, Power-Efficient Processors for Sensors and Embedded Systems

Margaret Martonosi，普林斯顿大学，传感器和嵌入式系统的自适应，高能效处理器传感器网络系统近年来受到越来越多的研究关注，具有广泛的科学和商业应用。传感器处理器需要“敏捷”的性能，快速响应高吞吐量突发，同时在可能的情况下降低能耗。传感器系统具有有限的功率预算，传统上大部分能量用于无线电通信。但随着无线电技术的进步和计算需求的增加，更多的能源预算又回到了处理器上。本研究探讨了传感器网络和其他嵌入式系统中用于敏捷、节能、基于流处理的处理器架构。一个特别的重点是使用并行（通过平铺处理单元）进行能源管理。另一个关键方面是研究片上处理单元之间的互连，并探索让不同处理单元以不同时钟频率运行的设计技术。例如，通过硬件队列系统连接处理元件，允许芯片利用基于线程的生产者-消费者模型来调整处理器设置以运行线程;这通过动态电压/频率缩放实现了有效的能量和速度控制。通过将队列/内存状态传递给近邻，处理器可以使用控制理论方法来协调本地和更广泛区域的性能/能量需求。主要的研究问题包括：（i）多少片上并行最好的平衡应用程序的性能和能源？(ii)该模型适用于哪些应用范围？(iii)如何基于局部和全局控制方法设计性能和功率效率高的速度控制模型？(iv)分布式和分级控制技术的作用是什么？(v)能否设计出在面对传感误差和传感/驱动延迟时具有良好响应性和稳定性的控制理论方法？

Margaret Martonosi, Princeton University, Adaptive, Power-Efficeint Processors for Sensors and Embedded Systems Sensor network systems have seen increasing research attention recently, with a wide range of scientific and commercial applications. Sensor processors need "agile" performance that responds quickly to high-throughput bursts, with also lower-energy execution whenpossible to minimize energy consumption. Sensor systems have limited power budgets, with traditionally most energy going to radio communications. But as radios improve and computationaldemands increase, more of the energy budget is shifting backto the processor.This research examines processor architectures for agile,energy-efficient, stream-based processing in sensor networksand other embedded systems. A particular focus is on usingparallelism (through tiled processing units) for energy management.Another key aspect is investigating the interconnect between on-chipprocessing units, and exploring design techniques that let differentprocessing elements run at different clock rates. Connecting processing elements by a system of hardware queues, for example, allows the chip to exploit a thread-based, producer-consumer model to adapt processor settingsto running threads; this enables efficient energy and speed controlvia dynamic voltage/frequency scaling. By exposingqueue/memory status to near neighbors, processors can usecontrol theoretic approaches to coordinate performance/energyneeds across local and broader regions. Major research questions include: (i) How much on-chip parallelismbest balances application performance and energy? (ii) What range of applications are applicable to this model? (iii) How to design performance andpower-efficient speed-control models based on local and globalcontrol approaches? (iv) What are the roles of distributed andhierarchical control techniques? (v) Can control theoreticapproaches be devised that offer good responsiveness and stabilityin the face of sensing errors and sensing/actuation delays?