Billion-Transistor Architectures

几十年来，微处理器的性能和片上密度都呈指数级增长。这种趋势没有减弱的迹象。然而，芯片间的通信成本并没有迅速提高，因此，如果目前的趋势继续下去，计算将越来越多地受到引脚带宽限制或外来封装成本的限制。这个项目的重点是架构，将解决新兴的带宽限制，以建立成本效益，高性能的系统。特别是，我们正在研究(1)未来的内存层次结构，在物理设计、逻辑组织和系统设计层面探索替代方案；(2)数据架构，利用冗余计算最小化通信需求；(3)混合并行执行，将DataScalar思想与并行线程相结合，同时支持多种计算模型。

Both microprocessor performance and on-chip densities have been growing exponentially for decades. This trend shows no signs of abatement. However, interchip communication costs are not improving nearly as rapidly, so that if present trends continue, computation will increasingly be limited by pin-bandwidth constraints, or by exotic packaging costs. This project is focused on architectures that will address the emerging bandwidth limitations in order to build cost- effective, high-performance systems. In particular, we are investigating (1) future memory hierarchies, exploring alternatives at the levels of physical design, logical organization, and system design; (2) DataScalar architectures, exploiting redundant computations to minimize communication requirements; and (3) Hybrid parallel execution, combining the DataScalar ideas with parallel threads to support multiple computation models simultaneously.