Adaptive Balanced Computing Architecture

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Applications, such as multimedia processing, digital signal, image and vision processing, and scientific computing, generate computation tasks that are structured and repetitive exhibiting varying degree of instruction-level parallelism (ILP). Moreover, the demands to compute certain functions and theirresource needs vary with applications and time. The overall goal of this project is to develop and use novel ideas such as reconfigurable functional units (FUs), cache memory, and reconfigurable bus architectures to achieve balanced computing, i.e. match the computing bandwidth to the memory bandwidth. The research will address issues in designing architectures that allow reconfiguration of resources to make the following architecture level parameters dynamically variable: number and types of FUs, amount of on-chip register and cache memory, an ability to trade the on-chip memory resources with the numberof FUs dynamically, and the interconnectivity between these units. A processor core with reconfigurable logic blocks to make the architecture adaptive to the applications' computing and memory bandwidth needs will be developed. Effects of integrating reconfiguration schemes into the on-chip FUs and cache memorieson a processor chip will also be studied and evaluated. A high-level design for the ABC (Adaptive Balanced Computing) architecture will be developed and analyzed. It is expected that the research results will significantly improve the efficiency of computation.