Error Detection and Recovery in High-Performance Fault-Tolerant Processor Systems Employing Caches

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Somani This is a project to mitigate the effects of transient faults in redundant computer systems that use cache memories. Redundant computer systems typically employ a voting circuit as part of the processor-memory interface to check for consistency in all bus transactions. If cache memories are used, many operations do not use the processor-memory interface, and so escape the scrutiny of the voter. In this project new cache protocols are being designed that provide for fault tolerance in redundant systems. The new protocols require the cache controllers to broadcast the contents of cache lines on occasion, and require cache controllers to respond to requests from the memory system to replace erroneous data. The project covers the development, analysis, and application of fault-tolerant cache protocols.