Error Detection and Recovery in High-Performance Fault-Tolerant Processor Systems Employing Caches

Somani这是一个项目，旨在减轻使用高速缓冲存储器的冗余计算机系统中的瞬时故障的影响。冗余计算机系统通常使用表决电路作为处理器-存储器接口的一部分，以检查所有总线事务中的一致性。如果使用高速缓冲存储器，许多操作不使用处理器-存储器接口，因此逃脱了投票者的审查。在这个项目中，正在设计新的高速缓存协议，以提供冗余系统中的容错。新协议要求高速缓存控制器偶尔广播高速缓存线的内容，并要求高速缓存控制器响应来自存储器系统的请求以替换错误数据。该项目涵盖容错缓存协议的开发、分析和应用。

Somani This is a project to mitigate the effects of transient faults in redundant computer systems that use cache memories. Redundant computer systems typically employ a voting circuit as part of the processor-memory interface to check for consistency in all bus transactions. If cache memories are used, many operations do not use the processor-memory interface, and so escape the scrutiny of the voter. In this project new cache protocols are being designed that provide for fault tolerance in redundant systems. The new protocols require the cache controllers to broadcast the contents of cache lines on occasion, and require cache controllers to respond to requests from the memory system to replace erroneous data. The project covers the development, analysis, and application of fault-tolerant cache protocols.