SBIR Phase I: Integrated Reactor Scale and Topography Feature Scale Simulator for Plasma Enhanced Semiconductor Processes

SBIR 第一阶段：用于等离子体增强半导体工艺的集成反应堆规模和形貌特征规模模拟器

• 批准号: 9960600
• 负责人: Phillip Stout
• 金额: $ 9.99万
• 依托单位: CFD RESEARCH CORPORATION
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-01-01 至 2000-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9960600&HistoricalAwards=false
• 关键词: SBIR; Phase; Integrated; Reactor; Scale

This Small Business Innovation Research Phase I project will develop a statistical (Monte Carlo) software model and software simulation tool for the pre-sheath and sheath regions of low pressure plasmas used in IC fabrication. The objective is to bridge the time/length scales between reactor scale phenomena and feature scale phenomena. The sheath models will be integrated with an existing reactor scale software model (CFD-ACE+) and feature scale software simulators (SPEEDIE and CATS). The work will fill a void currently faced by designers of plasma equipment and processes. It will evaluate the influence of macroscopic reactor conditions on feature scale profile evolution. Stanford University Center for Integrated Circuits will be a sub-contractor on this project. The Phase I effort will focus on an intermediate-scale model based on kinetic treatment of charged particle transport near the wafer surface. This model will be an interface between a hydrodynamic model in CFD-ACE+ and collisionless gas phase models in SPEEDIE and CATS for interstructure particle transport. The plasma-presheath model will provide spatially resolved distributions of ion flux, energy and angular distributions to SPEEDIE and CATS. Both SPEEDIE and CATS require die level models to resolve the impact of circuit layout/topography on species generation/loss, charged particle collection and currents paths to the substrate.In Phase II, the models will be refined and validated (against experiments conducted at Stanford) for silicon etch processes in Cl2 and SF6 systems. CATS will be expanded to include the wafer charging circuit and will be merged with SPEEDIE. The commercial availability of the capability will allow process engineers to design better processes and identify equipment/process deficiencies before physical prototyping. The use of the model will enable the reduction of potential yield losses due to unsatisfactory gap/step coverage, film noncomformality and undesirable etch profiles. According to industry observers, even a 2% improvement in the fabrication yield will provide significant savings to the industry.

这个小企业创新研究第一阶段项目将开发一个统计（蒙特卡罗）软件模型和软件模拟工具，用于在IC制造中使用的低压等离子体的前鞘和鞘区。 目的是在反应器规模现象和特征规模现象之间的时间/长度尺度上架起桥梁。 鞘层模型将与现有反应堆规模软件模型（CFD-ACE+）和特征规模软件模拟器（SPEEDIE和CATS）集成。 这项工作将填补目前等离子体设备和工艺设计者所面临的空白。 它将评估宏观反应堆条件对特征尺度剖面演变的影响。 斯坦福大学集成电路中心将是该项目的分包商。 第一阶段的努力将集中在一个中等规模的模型的基础上动力学处理附近的晶片表面的带电粒子运输。该模型将是CFD-ACE+中的流体动力学模型与SPEEDIE和CATS中的无碰撞气相模型之间的接口，用于结构间颗粒传输。等离子体预鞘模型将为SPEEDIE和CATS提供空间分辨的离子通量分布、能量分布和角分布。 SPEEDIE和CATS都需要芯片级模型来解决电路布局/形貌对物质产生/损失、带电粒子收集和到衬底的电流路径的影响。在第二阶段，将针对Cl 2和SF6系统中的硅蚀刻工艺对模型进行改进和验证（对照斯坦福大学进行的实验）。 CATS将扩展到包括晶圆充电电路，并将与SPEEDIE合并。 该能力的商业可用性将使工艺工程师能够设计更好的工艺，并在物理原型制作之前确定设备/工艺缺陷。 该模型的使用将能够减少潜在的产量损失，由于不满意的间隙/步骤覆盖，膜noncomformality和不良的蚀刻配置文件。 根据行业观察家的说法，即使制造产量提高2%，也将为行业节省大量资金。