SBIR Phase I: Integrated Reactor Scale and Topography Feature Scale Simulator for Plasma Enhanced Semiconductor Processes

这个小企业创新研究第一阶段项目将开发一个统计（蒙特卡罗）软件模型和软件仿真工具，用于IC制造中使用的低压等离子体的预鞘层和鞘层区域。目标是在反应器尺度现象和特征尺度现象之间架起时间/长度尺度的桥梁。护套模型将与现有的反应堆规模软件模型（CFD-ACE+）和特征规模软件模拟器（SPEEDIE和CATS）集成。这项工作将填补目前等离子设备和工艺设计人员面临的空白。评估宏观反应器条件对特征尺度剖面演化的影响。斯坦福大学集成电路中心将是该项目的分包商。第一阶段的工作将集中在基于晶圆表面带电粒子输运动力学处理的中等规模模型上。该模型将成为CFD-ACE+中的流体动力学模型与SPEEDIE和CATS中的无碰撞气相模型之间的接口，用于基础结构粒子输运。等离子体预鞘层模型将为SPEEDIE和CATS提供空间分辨的离子通量、能量和角分布。SPEEDIE和CATS都需要模具级模型来解决电路布局/地形对物质产生/损失，带电粒子收集和基片电流路径的影响。在第二阶段，将对Cl2和SF6系统中硅蚀刻工艺的模型进行改进和验证（对照斯坦福大学进行的实验）。CATS将扩展到晶圆充电电路，并将与SPEEDIE合并。该功能的商业可用性将允许工艺工程师设计更好的工艺，并在物理原型制作之前识别设备/工艺缺陷。使用该模型将能够减少由于不满意的间隙/步骤覆盖、薄膜不合格和不希望的蚀刻轮廓而造成的潜在产量损失。根据行业观察家的说法，即使是2%的制造成品率的提高也将为行业带来显着的节省。

This Small Business Innovation Research Phase I project will develop a statistical (Monte Carlo) software model and software simulation tool for the pre-sheath and sheath regions of low pressure plasmas used in IC fabrication. The objective is to bridge the time/length scales between reactor scale phenomena and feature scale phenomena. The sheath models will be integrated with an existing reactor scale software model (CFD-ACE+) and feature scale software simulators (SPEEDIE and CATS). The work will fill a void currently faced by designers of plasma equipment and processes. It will evaluate the influence of macroscopic reactor conditions on feature scale profile evolution. Stanford University Center for Integrated Circuits will be a sub-contractor on this project. The Phase I effort will focus on an intermediate-scale model based on kinetic treatment of charged particle transport near the wafer surface. This model will be an interface between a hydrodynamic model in CFD-ACE+ and collisionless gas phase models in SPEEDIE and CATS for interstructure particle transport. The plasma-presheath model will provide spatially resolved distributions of ion flux, energy and angular distributions to SPEEDIE and CATS. Both SPEEDIE and CATS require die level models to resolve the impact of circuit layout/topography on species generation/loss, charged particle collection and currents paths to the substrate.In Phase II, the models will be refined and validated (against experiments conducted at Stanford) for silicon etch processes in Cl2 and SF6 systems. CATS will be expanded to include the wafer charging circuit and will be merged with SPEEDIE. The commercial availability of the capability will allow process engineers to design better processes and identify equipment/process deficiencies before physical prototyping. The use of the model will enable the reduction of potential yield losses due to unsatisfactory gap/step coverage, film noncomformality and undesirable etch profiles. According to industry observers, even a 2% improvement in the fabrication yield will provide significant savings to the industry.