Noise Management for Systems-on-a-Chip

本计画主要针对数位/类比/射频积体电路中降低元件杂讯、基底杂讯耦合及电源杂讯耦合之建模、模拟与设计方法。模拟/数字/射频芯片中的噪声是通过了解这三种噪声源的贡献来探索的，这三种噪声源最初是在压控振荡器（VCO）的背景下，然后是在锁相环（PLL）中。VCO是一个很好的平台，为这项研究，因为它提出了一个最具挑战性的方面，射频和混合信号的设计。低相位噪声VCO设计的研究重点是（1）射频应用中谐振电路元件的详细寄生建模，（2）有源元件的噪声，以及（3）来自基板和电源的耦合噪声。模拟和设计技术正在开发，以预测和减少这些噪声源。本提案中的研究与一个重要的教育组成部分紧密结合，包括开发新课程和通过使用万维网传播研究相关成果和课程材料。

This project is on the development of modeling, simulation, and designapproaches for reducing device noise, substrate noise coupling, and supplynoise coupling in integrated digital/analog/RF ICs. Noise in analog/digital/RF chips is being explored by understanding the contributions ofthese three noise sources initially within the context of voltagecontrolled oscillators (VCOs) and then in phase locked loops (PLLs). TheVCO is a good platform for this study since it presents one of the mostchallenging aspects of RF and mixed-signal designs. Low phase noise VCOdesigns are being investigated with a focus on (1) detailed parasiticmodeling of the tank circuit elements for RF applications, (2) inclusion ofnoise due to the active elements, and (3) coupling noise from the substrateand power supply. Simulation and design techniques are being developed topredict and reduce these noise sources. The research in this proposal istightly integrated with a significant education component that includes thedevelopment of new courses and dissemination of both the research relatedresults and the course material through the use of the world wide web.