Noise Management for Systems-on-a-Chip

该项目旨在开发建模、仿真和设计方法，以降低集成数字/模拟/RF ic中的器件噪声、基板噪声耦合和电源噪声耦合。通过了解这三种噪声源的贡献，模拟/数字/射频芯片中的噪声正在被探索，首先是在压控振荡器（vco）的背景下，然后是在锁相环（pll）中。vco是本研究的一个很好的平台，因为它展示了射频和混合信号设计中最具挑战性的方面之一。低相位噪声vco设计正在被研究，重点是(1)射频应用的油箱电路元件的详细寄生建模，(2)由于有源元件引起的噪声的包含，以及(3)来自基片和电源的耦合噪声。模拟和设计技术正在发展，以预测和减少这些噪声源。本提案中的研究与重要的教育组成部分紧密结合，包括新课程的开发以及通过使用万维网传播与研究相关的结果和课程材料。

This project is on the development of modeling, simulation, and designapproaches for reducing device noise, substrate noise coupling, and supplynoise coupling in integrated digital/analog/RF ICs. Noise in analog/digital/RF chips is being explored by understanding the contributions ofthese three noise sources initially within the context of voltagecontrolled oscillators (VCOs) and then in phase locked loops (PLLs). TheVCO is a good platform for this study since it presents one of the mostchallenging aspects of RF and mixed-signal designs. Low phase noise VCOdesigns are being investigated with a focus on (1) detailed parasiticmodeling of the tank circuit elements for RF applications, (2) inclusion ofnoise due to the active elements, and (3) coupling noise from the substrateand power supply. Simulation and design techniques are being developed topredict and reduce these noise sources. The research in this proposal istightly integrated with a significant education component that includes thedevelopment of new courses and dissemination of both the research relatedresults and the course material through the use of the world wide web.