Inductance Control for On-Chip Signal Integrity

在0.25 mm及以下的晶体管几何尺寸下，片上电感成为重要的设计问题。 该项目的主要目标是生成计算机辅助设计工具和片上测量技术，使IC设计人员能够在不需要高度专业知识或实验的情况下科普电感相关问题。 该项目有三个重点。 在推力一，建模和模型简化技术将开发，使复杂的芯片上的结构进行建模和简化，使他们将易于模拟。 这些技术是基于规则的扩展PEEC和基于小波的提取。 第二个目标是建立一个自动化的方法来生成布局和性能裕度指南，供设计人员使用。 在这项工作的中心是识别一组广义参数化的互连拓扑结构，捕获电感控制相关的最重要的问题。 第三个推力涉及对其他两个推力的结果进行测量验证，并确定新的自动化原位测量技术。

On-chip inductance becomes an important design issue at transistor geometries of 0.25 mm and below. The primary goal of this project is to generate computer aided design tools and on-chip measurement techniques that will enable IC designers to cope with inductance related issues without the need for highly specialized knowledge or experimentation. The project has three thrusts. In thrust one, modeling and model reduction techniques will be developed that enable complex on-chip structures to be modeled and reduced so that they will be tractable for simulation. The techniques are based on rule-based extensions to PEEC and wavelet-based extraction. Thrust two is concerned with establishing an automated methodology to generate layout and performance margin guidance for use by designers. At the center of this effort is the identification of a set of generalized parameterized interconnect topologies that capture most of the important issues related to inductance control. Thrust three is concerned with measurement verification of the results of the other two thrusts and the determination of new automated in-situ measurement techniques.