Inductance Control for On-Chip Signal Integrity

片上电感成为0.25毫米及以下晶体管几何尺寸的重要设计问题。该项目的主要目标是生成计算机辅助设计工具和片上测量技术，使IC设计人员能够在不需要高度专业知识或实验的情况下处理电感相关问题。该项目有三个重点。在推力一，建模和模型简化技术将开发，使复杂的芯片结构建模和简化，使他们将是易于处理的模拟。这些技术基于基于规则的PEEC扩展和基于小波的提取。推力二是建立一个自动化的方法来生成布局和性能裕度指导，供设计师使用。这项工作的核心是识别一组广义参数化互连拓扑，这些拓扑捕获了与电感控制相关的大多数重要问题。第三次推力涉及对其他两次推力结果的测量验证和确定新的自动化原位测量技术。

On-chip inductance becomes an important design issue at transistor geometries of 0.25 mm and below. The primary goal of this project is to generate computer aided design tools and on-chip measurement techniques that will enable IC designers to cope with inductance related issues without the need for highly specialized knowledge or experimentation. The project has three thrusts. In thrust one, modeling and model reduction techniques will be developed that enable complex on-chip structures to be modeled and reduced so that they will be tractable for simulation. The techniques are based on rule-based extensions to PEEC and wavelet-based extraction. Thrust two is concerned with establishing an automated methodology to generate layout and performance margin guidance for use by designers. At the center of this effort is the identification of a set of generalized parameterized interconnect topologies that capture most of the important issues related to inductance control. Thrust three is concerned with measurement verification of the results of the other two thrusts and the determination of new automated in-situ measurement techniques.