Inductance Control for On-Chip Signal Integrity

当晶体管尺寸在0.25 mm及以下时，片上电感成为一个重要的设计问题。该项目的主要目标是生成计算机辅助设计工具和片上测量技术，使IC设计者能够处理与电感相关的问题，而不需要高度专业的知识或实验。该项目有三个推力。在第一推力中，将开发建模和模型简化技术，使复杂的片上结构能够被建模和简化，从而使它们易于处理以用于仿真。这些技术基于对PEEC的基于规则的扩展和基于小波的提取。推力二涉及建立一种自动化的方法，以生成供设计师使用的布局和性能余量指导。这项工作的核心是确定一组通用的参数化互连拓扑，这些拓扑捕获了与电感控制相关的大多数重要问题。推进器3涉及测量、验证其他两个推进器的结果以及确定新的自动化就地测量技术。

On-chip inductance becomes an important design issue at transistor geometries of 0.25 mm and below. The primary goal of this project is to generate computer aided design tools and on-chip measurement techniques that will enable IC designers to cope with inductance related issues without the need for highly specialized knowledge or experimentation. The project has three thrusts. In thrust one, modeling and model reduction techniques will be developed that enable complex on-chip structures to be modeled and reduced so that they will be tractable for simulation. The techniques are based on rule-based extensions to PEEC and wavelet-based extraction. Thrust two is concerned with establishing an automated methodology to generate layout and performance margin guidance for use by designers. At the center of this effort is the identification of a set of generalized parameterized interconnect topologies that capture most of the important issues related to inductance control. Thrust three is concerned with measurement verification of the results of the other two thrusts and the determination of new automated in-situ measurement techniques.