Ir02/(Ba,Sr)Ti03/Pt Storage Cells for 4 GBit DRAMs and Beyond: Ir, BST, and Selective Pt MOCVD and Interfacial Phenomena

用于 4 GBit DRAM 及以上的 Ir02/(Ba,Sr)Ti03/Pt 存储单元：Ir、BST 和选择性 Pt MOCVD 和界面现象

• 批准号: 0000121
• 负责人: Sandwip Dey
• 金额: $ 30万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-06-01 至 2003-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0000121&HistoricalAwards=false
• 关键词: Ir02; Ba; Sr; Ti03; Pt

Sandip DeyECS-0000121Barium strontium titanate, (Ba, Sr)TiO3 or BST, films with high permittivity are being considered for numerous applications including charge storage cells for 4, 16, and 64 gigabit (Gb) dynamic random access memories (DRAMs). The realization of Gb DRAMs with long refresh times is contingent upon the fabrication of electrically-reliable, trench IrO2/(Ba, Sr)TiO3/Pt storage cells on Si by manufacturable, metal-organic chemical vapor deposition (MOCVD) processes. Currently, the research efforts of our laboratory are focused on MOCVD of Ir, Pt, and BST, coupled with nanostructure evolution, electrical characterization, and modeling of interfaces. A critical issue that remain unresolved, which may eventually determine the refresh time, is the lack of understanding of the effects of interfacial space charge on the transient current and dielectric dispersion of the trench capacitor. Therefore, to realize mechanically robust, trench test cells, satisfying the geometric and electrical requirements of a 4 Gbit DRAM cell, a systematic and vertically-integrated program will be implemented to:a) fabricate trench IrO2/(BST)/Pt test cells on TaxSiyNz-passivated poly-Si plugs by sequential deposition of (i) Pt by MOCVD and/or sputtering, (ii) conformal BST by MOCVD, followed by photolithography, etching, and focused ion beam (FIB) milling of BST to define the geometry of one 4 Gbit cell, and (iii) conformal Ir by MOCVD followed by its oxidation, photolithography, and etchingb) quantitatively determine the space charge distribution at the Schottky BST/Pt interface in a test trench and its relationship to transient current, and dielectric dispersion by frequency and time domain techniquesc) optimize BST MOCVD parameters, from feedback of electrical characterization, by response surface analyses; fabricate cells with the required electrical performanceThe integration of the aforementioned ideas to fabricate the next generation of storage cells will be challenging but novel, and the concepts may well be extended to the 64 Gb level. A successful outcome will provide a solution for fabricating storage cells with longer refresh times. Arizona State University (ASU) is the appropriate place to initiate such an exciting research program. The PI has carried out research on MOCVD of dielectrics and metals, and interfacial phenomena in perovskite films over the last decade. An interdisciplinary approach will train personnel in a technologically important area, so that they can apply their science and engineering skills in the US industries and research laboratories upon completion.

具有高介电常数的钛酸锶钡（Ba，Sr）TiO 3或BST薄膜正被考虑用于许多应用，包括用于4、16和64吉比特（Gb）动态随机存取存储器（DRAM）的电荷存储单元。 具有长刷新时间的Gb DRAM的实现取决于通过可制造的金属有机化学气相沉积（MOCVD）工艺在Si上制造电可靠的沟槽IrO 2/（Ba，Sr）TiO 3/Pt存储单元。 目前，我们实验室的研究工作主要集中在金属有机化学气相沉积的Ir，Pt和BST，再加上纳米结构的演变，电特性，和建模的接口。 一个关键的问题，仍然没有得到解决，这可能最终决定刷新时间，是缺乏了解的瞬态电流和介电色散的沟槽电容器上的界面空间电荷的影响。 因此，为了实现机械上坚固的沟槽测试单元，满足4 Gbit DRAM单元的几何和电气要求，将实施系统的和垂直集成的程序，以：a）通过以下步骤在TaxSiyNz钝化的多晶硅插塞上制造沟槽IrO 2/（BST）/Pt测试单元：（i）通过MOCVD和/或溅射的Pt的顺序沉积，（ii）通过MOCVD的共形BST，随后通过光刻、蚀刻和BST的聚焦离子束（FIB）铣削，以限定一个4Gbit单元的几何形状，和（iii）通过MOCVD的共形Ir，随后通过其氧化、光刻，b）通过频域和时域技术定量确定测试沟槽中肖特基BST/Pt界面处的空间电荷分布及其与瞬态电流和介电色散的关系。c）通过响应面分析，根据电特性的反馈，优化BST MOCVD参数;制造具有所需电性能的单元将上述想法集成以制造下一代存储单元将是具有挑战性的但新颖的，并且这些概念很可能扩展到64 Gb级别。 成功的结果将为制造具有更长刷新时间的存储单元提供解决方案。 亚利桑那州立大学（ASU）是启动这样一个令人兴奋的研究计划的合适场所。 在过去的十年里，PI已经对钙钛矿和金属的MOCVD以及钙钛矿薄膜中的界面现象进行了研究。 跨学科的方法将在一个重要的技术领域培训人员，使他们能够在美国工业和研究实验室完成后应用他们的科学和工程技能。