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Ir02/(Ba,Sr)Ti03/Pt Storage Cells for 4 GBit DRAMs and Beyond: Ir, BST, and Selective Pt MOCVD and Interfacial Phenomena

Ir02/(Ba,Sr)Ti03/Pt Storage Cells for 4 GBit DRAMs and Beyond: Ir, BST, and Selective Pt MOCVD and Interfacial Phenomena
用于 4 GBit DRAM 及以上的 Ir02/(Ba,Sr)Ti03/Pt 存储单元:Ir、BST 和选择性 Pt MOCVD 和界面现象
批准号:
0000121
负责人:
Sandwip Dey
金额:
$30.0万
依托单位:
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2000
资助国家:
美国
项目状态:
已结题
起止时间:
2000-06-01 至 2003-12-31
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中文摘要
翻译
钛酸钡锶,(Ba, Sr)TiO3或BST,具有高介电常数的薄膜正被考虑用于许多应用,包括用于4,16和64gb动态随机存取存储器(dram)的电荷存储电池。实现具有长刷新时间的Gb dram取决于通过可制造的金属有机化学气相沉积(MOCVD)工艺在Si上制造电可靠的沟槽IrO2/(Ba, Sr)TiO3/Pt存储电池。目前,我们实验室的研究工作主要集中在Ir, Pt和BST的MOCVD,结合纳米结构演化,电学表征和界面建模。对于界面空间电荷对沟槽电容的瞬态电流和介电色散的影响缺乏理解,这是一个尚未解决的关键问题,它可能最终决定刷新时间。因此,为了实现机械坚固的沟槽测试电池,满足4 gb DRAM电池的几何和电气要求,将实施一个系统和垂直集成的计划:a)在taxsiynz钝化的多晶硅塞上通过顺序沉积(i)通过MOCVD和/或溅射沉积Pt, (ii)通过MOCVD保形BST,然后光刻,蚀刻,以及聚焦离子束(FIB)铣削BST以确定一个4gb电池的几何形状,以及(iii)通过MOCVD进行共形Ir,然后进行氧化,光刻和蚀刻;(b)定量确定测试沟槽中肖特基BST/Pt界面的空间电荷分布及其与瞬态电流和介电色散的关系)通过响应面分析从电特性反馈中优化BST MOCVD参数;集成上述想法来制造下一代存储单元将是具有挑战性的,但也是新颖的,并且这些概念很可能扩展到64gb级别。一个成功的结果将为制造具有更长的刷新时间的存储单元提供解决方案。亚利桑那州立大学(ASU)是启动这样一个令人兴奋的研究项目的合适场所。在过去的十年中,PI开展了介电介质和金属的MOCVD以及钙钛矿薄膜中的界面现象的研究。跨学科的方法将培养技术重要领域的人才,使他们能够在完成后将他们的科学和工程技能应用于美国的工业和研究实验室。
英文摘要
Sandip DeyECS-0000121Barium strontium titanate, (Ba, Sr)TiO3 or BST, films with high permittivity are being considered for numerous applications including charge storage cells for 4, 16, and 64 gigabit (Gb) dynamic random access memories (DRAMs). The realization of Gb DRAMs with long refresh times is contingent upon the fabrication of electrically-reliable, trench IrO2/(Ba, Sr)TiO3/Pt storage cells on Si by manufacturable, metal-organic chemical vapor deposition (MOCVD) processes. Currently, the research efforts of our laboratory are focused on MOCVD of Ir, Pt, and BST, coupled with nanostructure evolution, electrical characterization, and modeling of interfaces. A critical issue that remain unresolved, which may eventually determine the refresh time, is the lack of understanding of the effects of interfacial space charge on the transient current and dielectric dispersion of the trench capacitor. Therefore, to realize mechanically robust, trench test cells, satisfying the geometric and electrical requirements of a 4 Gbit DRAM cell, a systematic and vertically-integrated program will be implemented to:a) fabricate trench IrO2/(BST)/Pt test cells on TaxSiyNz-passivated poly-Si plugs by sequential deposition of (i) Pt by MOCVD and/or sputtering, (ii) conformal BST by MOCVD, followed by photolithography, etching, and focused ion beam (FIB) milling of BST to define the geometry of one 4 Gbit cell, and (iii) conformal Ir by MOCVD followed by its oxidation, photolithography, and etchingb) quantitatively determine the space charge distribution at the Schottky BST/Pt interface in a test trench and its relationship to transient current, and dielectric dispersion by frequency and time domain techniquesc) optimize BST MOCVD parameters, from feedback of electrical characterization, by response surface analyses; fabricate cells with the required electrical performanceThe integration of the aforementioned ideas to fabricate the next generation of storage cells will be challenging but novel, and the concepts may well be extended to the 64 Gb level. A successful outcome will provide a solution for fabricating storage cells with longer refresh times. Arizona State University (ASU) is the appropriate place to initiate such an exciting research program. The PI has carried out research on MOCVD of dielectrics and metals, and interfacial phenomena in perovskite films over the last decade. An interdisciplinary approach will train personnel in a technologically important area, so that they can apply their science and engineering skills in the US industries and research laboratories upon completion.
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