Smart Antennas and DS/CDMA Communications: Basic Algorithmic Developments and Hardware Prototyping

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0073660PadosAdaptive antenna arrays and DS/CDMA communication systems are two subjects with their own individual challenges that have separately generated significant research interest over the past several years. When brought together at the integrated antenna-arrayCDMA-receiver system level, these challenges are magnified and new problems of both theoretical and practical interest arise.This proposed research on antenna array DS/CDMA communicationsis characterized by the following three attributes: (i) The principle of joint space-time processing is maintained. (ii) Low optimization complexity is sought, therefore matrix inversions and/or eigen-decompositions are viewed as undesirable operations.(iii) Superior adaptive system performance on short data records,as opposed to ideal asymptotics, is the objective. In terms of projected contributions to science and engineeringprinciples, this proposed research is intended to build on past workof the PIs during the last four years -supported by seed funding by the National Science Foundation- that led to initial understanding andpreliminary development of new linear filter optimization criteria andprocedures. The focus is on low bias and low short-data-record variance adaptive optimization procedures that the investigators of this proposal have developed and termed ``auxiliary-vector (AV)'' filtering. AV filtering may touch many aspects of multidisciplinary engineering that are presentlyhampered by the ``curse of dimensionality'' and could benefit from adaptivefiltering and/or adaptive system optimization through limited input data.Variations of AV filtering schemes are currently considered in diversified areas that include temporal-only processing of CDMA signals, synchronization, adaptive robust spread-spectrum receiver designs, adaptive array radars,Direction-Of-Arrival estimation problems, and jam-resistant GPS. This presentresearch plan covers aspects varying from basic algorithmic developments and theoretical analysis to DSP and FPGA hardware prototyping and testing throughthe use of the SPW (R) block-level communications systems simulator, a programmable antenna array testbed with 12 complete receive chains, an anechoic chamber with range in excess of 7 meters, and a DSP/FPGA board-level implementation testbed.***