Additive Patterning of Integrated Functional Materials on a Chip

芯片上集成功能材料的增材图案化

• 批准号: 0088206
• 负责人: Nancy Sottos
• 金额: $ 45万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-09-15 至 2004-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0088206&HistoricalAwards=false
• 关键词: Additive; Patterning; Integrated; Functional; Materials

Nancy R. Sottos and David A. Payne, University of Illinois at Urbana-ChampaignProposal Number #0088206Additive Patterning of Integrated Functional Materials on a Chip A critical issue for the future engineering of microsystems on a chip is the ability to rapidly pattern dissimilar materials in complex integrated systems. A novel, additive method of patterning is proposed that will enable integration of functional materials (e.g., electrical, mechanical, optical, etc.) on a chip, rather than as a discrete component added into the circuit and system. Specifically, an interdisciplinary investigation is planned to examine additive patterning of integrated electroceramic thin film devices and to develop a better understanding of the complex residual stress development in the films during this process. Integration of electroceramic thin films is a key technology for the realization of future micro electromechanical (MEM) device applications such as miniaturized sensors and actuators, ultrasonic motors and optical elements as well as nonvolatile memory elements and switching capacitors for integrated circuitry. In order to advance this technology for the next generation of electromechanical devices, it is essential to develop a fundamental understanding of the residual stresses generated in the films during patterning, the effects of these stresses on film properties and how to tailor these stresses for optimal device performance. Specific goals of this interdisciplinary investigation include: (i) development of new protocols to pattern thicker electroceramic films and multilayer devices where residual stresses are most critical, (ii) in-situ measurement of residual stress development during patterning, (iii) development of analytical models to understand the role of the substrate, film adhesion, and processing conditions on residual stress, (iv) characterization of the electromechanical properties of patterned films and assess the effects of residual stress on performance, and (v) development of a strategy for tailoring the residual stress state for optimal performance and reliability of the device.

南希河Sottos和大卫A. Payne，University of Illinois at Urbana-ChampaignProposal Number #0088206Additive Patterning of Integrated Functional Materials on a Chip未来芯片上微系统工程的一个关键问题是在复杂集成系统中快速图案化不同材料的能力。 提出了一种新颖的、附加的图案化方法，该方法将使得能够集成功能材料（例如，电气、机械、光学等）在芯片上，而不是作为添加到电路和系统中的分立元件。 具体而言，计划进行跨学科的调查，以检查添加剂图案化的集成电瓷薄膜器件，并制定一个更好的理解在这个过程中的膜中的复杂的残余应力的发展。 电子陶瓷薄膜的集成是实现未来微机电（MEM）器件应用的关键技术，例如微型传感器和致动器、超声马达和光学元件以及用于集成电路的非易失性存储器元件和开关电容器。 为了推进这一技术的下一代机电设备，它是必不可少的发展过程中产生的残余应力的膜图案，这些应力对膜性能的影响，以及如何定制这些应力的最佳设备性能的基本理解。 这一跨学科研究的具体目标包括：（i）开发新的方案以图案化较厚的电陶瓷膜和多层器件，其中残余应力是最关键的，（ii）在图案化期间残余应力发展的原位测量，（iii）开发分析模型以理解衬底、膜粘附和处理条件对残余应力的作用，（iv）表征图案化膜的机电性质并评估残余应力对性能的影响，以及（v）开发用于定制残余应力状态以获得器件的最佳性能和可靠性的策略。