SGER: Investigation of Microwave Components on CMOS Substrate for a Wireless Chip-to-Chip Interconnect System

SGER：针对无线芯片到芯片互连系统的 CMOS 基板上的微波组件的研究

• 批准号: 0095245
• 负责人: Ioannis Papapolymerou
• 金额: $ 4.88万
• 依托单位: University of Arizona
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-09-01 至 2001-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0095245&HistoricalAwards=false
• 关键词: SGER; Investigation; Microwave; Components; CMOS

0095245PapapolymerouMicrowave and mm-wave circuit technology that offers high-performance, low cost, small size and high profit is essential for today's cost driven commercial and military industries. In order to meet the above requirements, the research community during the last five years has been focusing on entire system-on-a-chip solutions, where both passive and active components are monolithically integrated on a single semiconductor substrate (Si, GaAs, SiGe) for dense, miniature lightweight and highly reliable microwave systems. The above solutions will also lead to analog, digital, MEMS and microwave circuits co-existing on a single chip that is capable to sense, think, act and communicate. This concept can be used for the development of microwave/mm-wave circuit-to-circuit interconnects that overcome many of the problems associated with traditional interconnect techniques and address future demands for feature sizes less than 100 nm.Currently, wire bond and flip chip interconnects are large compared to dimensions used in microelectronic fabrication technologies and cannot meet the signal delay and clock speed requirements beyond the 100 mn node. Guided-wave interconnects using metal traces also pose serious limitations due to propagation delay, signal distortion, noise and losses. Furthermore, they impose a serious limitation on circuit density and cost and can introduce parasitic reactances that degrade circuit performance. Wireless interconnects, on the other hand, eliminate the need for increased wire density and do not suffer from loss related to finite interconnect conductivity. Parasitic effects, such as crosstalk, are reduced and time delays can also be minimized if a fast conversion scheme that translates the base signal to an RF one is used. In this project, the PI proposes to investigate both theoretically and experimentally the basic microwave components of a wireless chip-to-chip interconnect system operating between 30 and 35 GHz. These components will reside on top of a low resistivity (CMOS) silicon wafer covered with a thin dielectric layer such as polyimide. The microwave circuits will be designed with Finite Ground Coplanar (FGC) line elements that can support TEM mode propagation and have a loss that is predominantly ohmic. The philosophy of the system is the following: An oscillator at 30-35 GHz will feed a planar phase shifter that utilizes MEMS bridges to change the phase of the microwave signal that is then transmitted by a slot antenna. The digital bit stream is applied as a positive modulating voltage to the MEMS phase shifter producing a microwave signal with BPSK modulation. At the receiving chip the phase of the incoming microwave signal (received with a slot antenna) will be compared to a reference signal via a phase detector (mixer) that will demodulate the BPSK microwave signal. A bandpass filter is used right after the receiving slot antenna to isolate the frequency of interest. Due to the high risk nature of the proposed research, the study of three passive components (slot antenna, MEMS phase shifter and bandpass filter) on CMOS silicon wafers will be pursued under an SGER grant. The three microwave circuits will be characterized experimentally with on-wafer measurements and theoretically with full-wave simulations. The main research effort will focus on understanding the properties and performance implications and limitations of the three passive microwave circuits residing on top of a low resistivity silicon substrate, with a goal to optimize their response. For the phase shifter, the characteristics of the MEMS switches on top of a CMOS wafer will also be explored and their interaction with it will be analyzed. It is anticipated that the proposed research will result in significant contributions to the area of integrated microwave and digital systems-on-a-chip and wireless interconnects, as well as provide valuable insights for the design of FGC microwave circuits on CMOS substrates used for digital circuitry.

0095245 Papapolymerus微波和毫米波电路技术提供高性能、低成本、小体积和高利润，对于当今成本驱动的商业和军事行业至关重要。为了满足上述要求，过去五年中，研究界一直专注于整个片上系统解决方案，即将无源和有源组件单片集成在单个半导体衬底(Si、GaAs、SiGe)上，以实现高密度、小型化、轻量化和高可靠性的微波系统。上述解决方案还将使模拟、数字、MEMS和微波电路共存于能够感知、思考、行动和通信的单一芯片上。这一概念可用于开发微波/毫米波电路到电路互连，克服与传统互连技术相关的许多问题，并满足未来对特征尺寸小于100 nm的需求。目前，与微电子制造技术中使用的尺寸相比，线键合和倒装芯片互连较大，无法满足100mN节点以外的信号延迟和时钟速度要求。由于传输延迟、信号失真、噪声和损耗，使用金属迹线的导波互连也造成了严重的限制。此外，它们对电路密度和成本施加了严重限制，并可能引入降低电路性能的寄生电抗。另一方面，无线互连消除了增加线路密度的需要，并且不会受到与有限的互连传导性相关的损耗的影响。如果使用将基本信号转换为RF信号的快速转换方案，则可以减少诸如串扰等寄生效应，并且还可以最小化时间延迟。在这个项目中，PI建议从理论和实验两个方面研究工作在30到35 GHz之间的无线芯片到芯片互连系统的基本微波组件。这些组件将位于覆盖着聚酰亚胺等薄介电层的低电阻率(Cmos)硅片的顶部。微波电路将采用有限接地共面(FGC)线元件设计，这些元件可以支持TEM模式的传播，并且具有主要为欧姆的损耗。该系统的原理如下：30-35 GHz的振荡器将馈送平面移相器，移相器利用MEMS桥改变微波信号的相位，然后通过缝隙天线传输。数字比特流作为正调制电压施加到MEMS移相器，产生具有BPSK调制的微波信号。在接收芯片处，输入微波信号(用缝隙天线接收)的相位将通过鉴相器(混频器)与参考信号进行比较，该鉴相器将解调BPSK微波信号。在接收缝隙天线之后使用带通滤波器来隔离感兴趣的频率。由于拟议研究的高风险性质，三个无源元件(缝隙天线、MEMS移相器和带通滤波器)的研究将在SGER拨款下进行。这三个微波电路将通过晶片上的测量和理论上的全波模拟来进行实验表征。主要的研究工作将集中在了解三种位于低阻硅衬底上的无源微波电路的特性、性能影响和限制，目的是优化它们的响应。对于移相器，我们还将探讨位于芯片顶端的MEMS开关的特性，并分析它们与移相器的相互作用。预计拟议的研究将对集成微波和数字单片系统以及无线互连领域做出重大贡献，并为用于数字电路的CMOS衬底上的FGC微波电路的设计提供有价值的见解。