Via-Arrays in Multilayer Substrates for Usage in High-Speed, Energy- and Resource-Efficient Digital Systems

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In this follow-up project an existing algorithm for fast modeling of via-arrays shall be improved on the basis of newly gained insights and shall be applied to the analysis of energy- and resource-efficient digital systems. Via-arrays are regular arrangements of up to several thousand vertical through-holes in multilayer substrates, like printed circuit boards and multi-chip modules, and pose a serious challenge to the design process. The project has the following two main goals: First, the further acceleration of the existing algorithm by making use of the existing redundancies in the matrices that describe the via-array behavior. Here, the arithmetic for hierarchical matrices (so called H-matrices) shall be applied to implement routines with reduced computational effort for matrix inversion, matrix-matrix multiplication and further operations. Due to inherent redundancies of via-array modeling (for example owing to the multitude of identical via distances) it can be expected in principle that hierarchical matrices can be applied successfully. For the construction of H-matrices and for the application of the mentioned operations the HLIB by Max Planck Institute for Mathematics in the Sciences from Leipzig is available and shall be used as a basis for own programming. Second, the extension and adaptation of the existing algorithm in view of the challenges of via-array optimization. Elements of this work are the implementation of suitable network ports in multilayer substrates, the automatic design of fan-out alternatives (wirings) for via-arrays and the automatic analysis of link data (e.g. bit error rates) for generation of optimization criteria.Both goals contribute to a direct continuation of the original research program and will advance and complete it with new insights gained in recent years.