Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Advanced CMOS for Mixed-Mode Systems

混合信号电子技术研究：NSF 和 SRC 的联合倡议：用于混合模式系统的高级 CMOS

• 批准号: 0120366
• 负责人: Jason Woo
• 金额: $ 22.5万
• 依托单位: University of California-Los Angeles
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-08-15 至 2004-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0120366&HistoricalAwards=false
• 关键词: Research; Mixed; Signal; Electronic; Technologies

0120366WooThe PIs propose to investigate the design of CMOS devices, circuits, and architectures in the sub-100nm regime with emphasis on high-performance mixed-signal, and RF applications. The thrust of this work will be device/circuit/architecture co-design targeting critical building blocks of mixed-mode systems. The goals are (1) to understand the fundamental device/circuit issues of deeply scaled CMOS, and (2) investigate and develop novel device engineering with novel thin film materials and new circuit architectures that will enable much superior speed, power, and noise performance.Recently, there is much discussion concerning the scaling of MOSFETs into sub-100nm dimensions. Topics such as alternative high-k gate dielectrics, gate leakage, shallow junction formation, source/drain extension engineering, and channel doping engineering are under intensive investigation. Many fundamental device problems such as short channel effects (DIBL and VTH roll-off), off-state leakage current, parasitic capacitance and resistance, and gate tunneling current are currently being examined. It is apparent that sub-50nm transistors can be realized with very high performance limited primarily by parasitics such as series resistance and capacitance. The challenge is mainly how to reduce the off current. This is fundamentally due to the electro-static coupling between the channel region and the source/drain. Although the PIs can reduce the coupling by scaling the junction depth, the ultra-shallow junction implies high series resistance and worse transistor performance. In order to expand the device-design window and toovercome the above-mentioned difficulties, novel device structures and new material systems need to be explored.So far, most of the advance device technology studies have concentrated on digital applications despite the growing interest in RF CMOS and high-speed mixed-mode circuits for communication and multimedia applications. Until now, technology development does not adequately address the issues of concern to analog circuits. Device models are also not sufficient for accurate circuit simulation. In this project, they propose to investigate the design of CMOS devices, circuits, and architectures in the sub-100nm regime with emphasis on high-performance mixed-signal, and RF applications. They propose to study the "analog nonidealities" of short-channel devices, e.g., gate current, nonlinearity, noise, intrinsic gain, variation of output impedance with the drain-source voltage. CMOS on SOI has been suggested as an alternative to bulk CMOS in sub-150nm regime. In the case of digital applications, the key advantage is probably in low-power circuits. For analog circuits, the choice of partially-depleted technology versus fully-depleted technology is still under debate. In the case of RF applications, the small parasitic capacitance of SOI CMOS is particularly attractive. However, many issues related to the floating body need to be clarified. In this project, the PIs will examine the many issues, such as noise, frequency performance, gain, and linearity of SOI MOSFETs for use in high-speed analog circuits. They will also examine novel sub-50nm device structures such as SiGe CMOS, low noise (buried channel) CMOS on SOI, high-performance LBJT as well as DTCMOS. In the case of SiGe, by having the smaller bandgap SiGe source/drain regions, the built-in potential is reduced and can substantially reduce the DIBL and other short channel effects. In addition, the higher mobilities can also improve the source/drain series resistances.

0120366WooPI建议研究亚100 nm范围内的CMOS器件、电路和架构的设计，重点是高性能混合信号和射频应用。这项工作的主旨将是以混合模式系统的关键构建块为目标的设备/电路/架构联合设计。其目标是(1)了解深尺寸CMOS的基本器件/电路问题，(2)利用新的薄膜材料和新的电路结构来研究和开发新的器件工程，以实现更高的速度、功耗和噪声性能。最近，关于将MOSFET尺寸扩展到100 nm以下的讨论很多。诸如交替高k栅电介质、栅漏、浅结形成、源/漏扩展工程和沟道掺杂工程等主题正在深入调查中。目前正在研究许多基本的器件问题，例如短沟道效应(DIBL和VTH滚降)、关态泄漏电流、寄生电容和寄生电阻以及栅隧道电流。显然，亚50 nm晶体管可以实现非常高的性能，主要受串联电阻和电容等寄生因素的限制。挑战主要是如何减少关断电流。这基本上是由于沟道区和源极/漏极之间的静电耦合。虽然PI可以通过调整结深来减少耦合，但超浅结意味着高串联电阻和较差的晶体管性能。为了扩大器件设计的窗口，克服上述困难，需要探索新的器件结构和新的材料体系。尽管人们对用于通信和多媒体应用的射频CMOS和高速混合模式电路越来越感兴趣，但到目前为止，大多数先进器件技术的研究都集中在数字应用上。到目前为止，技术发展还不足以解决模拟电路所关心的问题。器件模型也不足以进行准确的电路模拟。在这个项目中，他们建议研究亚100纳米范围内的CMOS器件、电路和架构的设计，重点是高性能混合信号和射频应用。他们建议研究短沟道器件的“模拟非理想性”，例如栅极电流、非线性、噪声、本征增益、输出阻抗随漏极-源极电压的变化。SOI上的CMOS已被建议作为亚150 nm区的体CMOS体的替代方案。在数字应用的情况下，关键的优势可能是低功耗电路。对于模拟电路，选择部分耗尽技术还是完全耗尽技术仍在争论中。在射频应用的情况下，SOI CMOS的小寄生电容特别吸引人。然而，与浮体相关的许多问题需要澄清。在本项目中，PI将检查用于高速模拟电路的SOI MOSFET的许多问题，如噪声、频率性能、增益和线性度。他们还将研究新的亚50 nm器件结构，如SiGe CMOS、SOI上的低噪声(掩埋沟道)CMOS、高性能LBJT以及DTCMOS。在SiGe的情况下，通过具有较小的带隙SiGe源/漏区，降低了内置电势，并且可以显著降低DIBL和其他短沟道效应。此外，较高的迁移率还可以改善源漏串联电阻。