Rugged, Compact, Modular OEIC Co-Processor

该研究计划的目标是开发算法和体系结构，并制造和演示一个坚固、紧凑、模块化、多功能、光学电子、集成电路(OEIC)神经网络和模糊逻辑协处理器系统，该系统将与标准PC微处理器一起工作。这种OEIC协处理器将比标准PC微处理器更有效地执行复杂的并行和/或模糊处理操作。建议的OELC协处理器的大小约为CD-ROM驱动器的大小，因此可以很容易地放入传统个人计算机的机箱中。为了证明协处理器的可行性，建议的硬件开发任务包括：(I)设计、制造和表征新型的2-D阵列的GaAs-SOS(蓝宝石上的硅)OEIC级联智能像素，每个像素中具有探测器、集成电路逻辑和光源(在计划的头两年中，谐振腔发光二极管(RCLED)，以及在第三年中用垂直腔面发射激光器(VCSELs)取代RCLED)，(2)设计，基于布拉格全息位相光栅阵列的新型可重构光学互连元件的制备和表征，(3)对准(在掩模对准器的帮助下)和粘合协处理器(OEIC)的所有组件。互连元件和输出光电探测器阵列)一起组成坚固、紧凑、模块化的多层夹层结构，以永久解决任何微光学对准问题，以及(4)表征由此产生的高速、多层光电协处理器。该计划的早期重点将放在神经网络配置上。因此，除了上述制造任务外，PI还将执行以下理论、建模和仿真任务：(A)开发算法，特别是那些适用于可编程最近邻互连(例如脉冲耦合网络)的算法，以解决一大类多维信息处理问题，以及(B)探索这些新型协处理器在三种不同类型的问题上的应用：(I)基于联想记忆的模式识别，(Ii)医学图像分割和(Iii)将一组低对比度光谱偏振红外图像融合成单一的高对比度图像。

The objective of this research program is to develop algorithms and architectures, and fabricate and demonstrate a rugged, compact, modular, versatile, opt electronic, integrated-circuit (OEIC) neural network and fuzzy logic coprocessor system that would work in conjunction with the standard PC microprocessor. This OEIC co-processor will perform sophisticated parallel and/or fuzzy processing operations more efficiently than the standard PC microprocessor. The proposed OElC co-processor will be about the size of a CD-ROM drive, and thus would fit easily inside the case of a conventional personal computer. Another important goal of the program is that this compact OEIC co-processor be amenable to mass manufacturing.To demonstrate the feasibility of the co-processor, the proposed hardware development tasks include: (I) design, fabrication and characterization of novel 2-D arrays of GaAs-SOS (silicon-on sapphire) OEIC cascadable smart pixels with a detector, integrated-circuit logic and a light source in each pixel (resonant cavity light-emitting diodes (RCLEDs) in the first two years of the program, and vertical-cavity surface-emitting lasers (VCSELs) replacing the RCLEDs in the third year), (2) design, fabrication and characterization of novel reconfigurable optical interconnection elements based on arrays of Bragg-holographic phase gratings, (3) aligning (with the help of a mask aligner) and gluing all the components of the co-processor (OEICs. interconnection elements, and output photodetector array) together into a rugged, compact, modular multi-layer sandwich configuration so as to permanently solve any micro-optics alignment problems, and (4) characterizing the resulting high-speed, multilayer optoelectronic co-processor. The early focus of the program will be on neural network configurations. So in addition to the above-mentioned fabrication tasks, the PI will also carry' out the following theoretical, modeling and simulation tasks: (a) develop algorithms, especially those suitable for programmable nearest-neighbor interconnections (e.g. pulse-coupled networks) to solve a large class of multi-dimensional information processing problems, and (b) explore the application of these novel co-processors to three different types of problems: (i) associative-memory-based pattern recognition, (ii) medical image segmentation and (iii) fusion of a set of low-contrast spectro-polarimetric infrared images into a single high-contrast image.