Rugged, Compact, Modular OEIC Co-Processor

坚固、紧凑、模块化 OEIC 协处理器

• 批准号: 0202487
• 负责人: Cardinal Warde
• 金额: --
• 依托单位: Massachusetts Institute of Technology
• 依托单位国家: 美国
• 项目类别: Continuing grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-10-01 至 2007-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0202487&HistoricalAwards=false
• 关键词: Rugged; Compact; Modular; OEIC; Co

The objective of this research program is to develop algorithms and architectures, and fabricate and demonstrate a rugged, compact, modular, versatile, opt electronic, integrated-circuit (OEIC) neural network and fuzzy logic coprocessor system that would work in conjunction with the standard PC microprocessor. This OEIC co-processor will perform sophisticated parallel and/or fuzzy processing operations more efficiently than the standard PC microprocessor. The proposed OElC co-processor will be about the size of a CD-ROM drive, and thus would fit easily inside the case of a conventional personal computer. Another important goal of the program is that this compact OEIC co-processor be amenable to mass manufacturing.To demonstrate the feasibility of the co-processor, the proposed hardware development tasks include: (I) design, fabrication and characterization of novel 2-D arrays of GaAs-SOS (silicon-on sapphire) OEIC cascadable smart pixels with a detector, integrated-circuit logic and a light source in each pixel (resonant cavity light-emitting diodes (RCLEDs) in the first two years of the program, and vertical-cavity surface-emitting lasers (VCSELs) replacing the RCLEDs in the third year), (2) design, fabrication and characterization of novel reconfigurable optical interconnection elements based on arrays of Bragg-holographic phase gratings, (3) aligning (with the help of a mask aligner) and gluing all the components of the co-processor (OEICs. interconnection elements, and output photodetector array) together into a rugged, compact, modular multi-layer sandwich configuration so as to permanently solve any micro-optics alignment problems, and (4) characterizing the resulting high-speed, multilayer optoelectronic co-processor. The early focus of the program will be on neural network configurations. So in addition to the above-mentioned fabrication tasks, the PI will also carry' out the following theoretical, modeling and simulation tasks: (a) develop algorithms, especially those suitable for programmable nearest-neighbor interconnections (e.g. pulse-coupled networks) to solve a large class of multi-dimensional information processing problems, and (b) explore the application of these novel co-processors to three different types of problems: (i) associative-memory-based pattern recognition, (ii) medical image segmentation and (iii) fusion of a set of low-contrast spectro-polarimetric infrared images into a single high-contrast image.

本研究计划的目标是开发算法和架构，制造和演示一个坚固的，紧凑的，模块化的，多功能的，光学电子，集成电路（OEIC）神经网络和模糊逻辑协处理器系统，将与标准的PC微处理器一起工作。这种OEIC协处理器将比标准PC微处理器更有效地执行复杂的并行和/或模糊处理操作。拟议中的OELC协处理器的大小将与CD-ROM驱动器相当，因此很容易安装在传统个人计算机的机箱内。该计划的另一个重要目标是使这种紧凑的OEIC协处理器能够大规模生产。为了证明协处理器的可行性，建议的硬件开发任务包括：（I）新型二维GaAs SOS阵列的设计、制备和表征（硅基蓝宝石）带探测器的OEIC可重复智能像素，集成电路逻辑和光源（在该计划的前两年是谐振腔发光二极管（RCLED），在第三年是垂直腔面发射激光器（VCSEL）取代RCLED），（2）设计，基于布拉格全息相位光栅阵列的新型可重构光互连元件的制造和表征，（3）对准（在掩模对准器的帮助下）和胶合协处理器（OEIC）的所有组件。互连元件和输出光电检测器阵列）一起形成坚固、紧凑、模块化的多层夹层结构，以便永久地解决任何微光学器件对准问题，以及（4）表征所得的高速多层光电协处理器。该计划的早期重点将是神经网络配置。因此，除了上述制造任务外，PI还将执行以下理论、建模和仿真任务：（a）开发算法，特别是适用于可编程最近邻互连的算法（例如脉冲耦合网络）来解决一大类多维信息处理问题，以及（B）探索这些新颖的协处理器对三种不同类型的问题的应用：（i）基于联想记忆的模式识别，（ii）医学图像分割和（iii）将一组低对比度光谱偏振红外图像融合成单个高对比度图像。