ITR: Dynamically Tunable Clustered Multithreaded Architectures

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The goal of the proposed research is to efficiently exploit on-chip parallelism via the design and evaluation of a dynamically tunable clustered multithreaded (DT-CMT) architecture. The proposed architecture will combine the utilization advantages of simultaneous multithreaded architectures (SMTs) with the speed advantages of chip multiprocessors (CMPs). The PIs will design an architecture that can be rapidly configured into a restricted number of organizations (so as to minimize speed and density impact) in order to balance instruction-level parallelism and thread-level parallelism to maximize utilization and minimize energy. Key to this approach will be the development of software systems (compilers, runtime systems, multiprogramming and multithreaded support) that analyze application requirements and combine thisknowledge with feedback mechanisms from the hardware. The performance and power saving potential of this approach will be characterized via simulation.This project has the potential to significantly impact the microarchitecture and software of future server and network processors, and will help train the graduate students in the design of future increasingly process technology-aware architectures. The proposed work will allow dynamic tailoring of the processorarchitecture in order to meet the needs of increasingly diverse applications, thereby allowing future processors to scale as process technology improves.