Communication and Synchronization Mechanisms for Emerging Multi-Core Processors

新兴多核处理器的通信和同步机制

• 批准号: 0702505
• 负责人: Sandhya Dwarkadas
• 金额: --
• 依托单位: University of Rochester
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-09-01 至 2010-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702505&HistoricalAwards=false
• 关键词: Communication; Synchronization; Mechanisms; Emerging; Multi

CCF-CPA: Communication and Synchronization Mechanisms for Emerging Multi-Core ProcessorsSandhya Dwarkadas and Michael L. ScottMarch 2007As a result of increasing chip density and power limitations, explicit hardware parallelism will soon dominate the computing spectrum, with multicore chips replacing uniprocessors throughout the desktop andlaptop markets. If these chips are to be used effectively, new programming models must ease the task of writing multithreaded code. These models must in turn be supported by architectural mechanisms thatminimize the cost of data communication and synchronization.The sponsored research addresses the challenge of mainstream parallelism using a combined hardware-software approach. The key idea is to identify common time-critical operations, across a variety of applications and programming models, that might be accelerated or simplified by new architectural mechanisms, and then to design those mechanisms in as general a fashion as possible. By leaving policy tosoftware whenever possible, this strategy aims to maximize opportunities for adaptive and application-specific protocols that increase scalability. Candidate hardware mechanisms include alert-on-update, which leverages cache coherence for fast event-based communication; programmable data isolation, which allows a processor to hide local writes for speculation and transactions; and adaptive cooperative caching, which re-engineers the on-chip coherence protocol to accommodate different patterns of data sharing and to communicate values efficiently between cores. These mechanisms will be studied mainly at the hardware level, but system software will also be developed to support new programming models (transactions, speculation) and to enable detailed evaluation of performance and programmability.Through better parallel programming models and efficient implementations, the sponsored research aims to continue the computing revolution over the course of the coming decade. By enabling the effective use of larger numbers of simpler cores, it also addresses the critical need to reduce energy consumption in mainstream processors. Driving applications will be drawn from multiple sources, including collaborative efforts with University colleagues in Biology, Astrophysics, and Chemistry; department colleagues in Artificial Intelligence and Internet services; and local and remote colleagues in data mining. Programming models and tasks will include transactional computing, speculative execution, and performance and correctness debugging.

CCF-CPA：新兴多核处理器的沟通和同步机制，以及Michael L. Scottmarch 2007年，这是由于芯片密度增加和功率限制的结果，显式硬件并行性将很快在整个台式台球上替换了多芯片芯片，并将在多层芯片上占据计算频谱。 如果要有效地使用这些芯片，则新的编程模型必须简化编写多线程代码的任务。这些模型反过来又必须由建筑机制来支持数据通信和同步的成本。赞助研究通过使用组合的硬件软件方法来解决主流并行性的挑战。 关键思想是在各种应用程序和编程模型中识别常用时间关键操作，这些操作可能会通过新的建筑机制加速或简化，然后尽可能一般地设计这些机制。 通过尽可能离开策略Tosoftware，该策略旨在最大限度地提高自适应和应用程序特定协议的机会，以提高可扩展性。 候选硬件机制包括通风前的日期，利用高速缓存相干来基于事件的通信；可编程数据隔离，该数据允许处理器隐藏本地写作，以进行投机和交易；和自适应合作缓存，该缓存重新设计了片上连贯协议，以适应不同的数据共享模式并在核心之间有效地传达价值。 这些机制将主要在硬件级别上进行研究，但是还将开发系统软件以支持新的编程模型（交易，猜测），并能够详细评估性能和可编程性。通过更好的并行编程模型和有效的实现，这些赞助的研究目标是在未来十年的时间内继续进行计算革命。 通过有效利用大量简单的核心，它还解决了减少主流处理器能源消耗的关键需求。驾驶申请将来自多种来源，包括与大学同事在生物学，天体物理学和化学方面的合作；人工智能和互联网服务的部门同事；以及数据挖掘的本地和远程同事。 编程模型和任务将包括交易计算，投机执行以及性能和正确性调试。