NER: Hierarchical self-assembly of DNA tiles

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What we will do: Five levels of hierarchical self-assembly will be used to control the placement of single nanoparticles and inorganic molecules over areas that are hundreds of microns in size. Self-assembly and enzymatic processing steps will be used to createDNA tiles1 and multi-tile "rafts" that have dimensions in the 4-60 nm size range. The tiles will contain derivatization sites at known spatial locations to permit attachment of non-DNA components. Up to six different molecules or nanoparticles could be attached to each DNA tile. Molecular liftoff2 will be used to direct the binding of the DNA rafts to lithographic features, such as 30 nm lines. The dimensions of the DNA rafts are similar to the dimensions of the lithographic features, so individual molecules that are attached to the rafts will be placed on the surface with great control and could be located near other lithographic structures. These capabilities would be very useful for construction of molecular quantum-dot cellular automata circuits and other molecular electronic devices.Intellectual Merit: This project will: -explore hierarchical design as a tool for creation of supramolecular complexity -extend molecular liftoff, which has previously been used only for small inorganic molecules, to biomolecules such as DNA. -integrate top-down and bottom-up approaches to the fabrication of structures on the nanometer to micron size scaleBroader impact: This proposal combines detailed control over local physical structure with ultra-high resolution nanolithography to create non-repetitive arrays of the types required for large-scale implementation of different architectures for molecular electronics.3 DNA will be used as a self-assembling circuit board for active components, which could include nanoparticles, other biomolecules, and small organic or inorganic molecules. This method could be used to construct technologically useful devices, such as molecular electronic field-programmable gate arrays that are integrated with I/O structures on a silicon chip.