ITR/NGS: High-Performance Configurable Hardware Using Liquid Architecture

ITR/NGS：使用 Liquid 架构的高性能可配置硬件

• 批准号: 0313203
• 负责人: Ron Cytron
• 金额: $ 49.48万
• 依托单位: Washington University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-09-15 至 2007-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0313203&HistoricalAwards=false
• 关键词: ITR; NGS; Performance; Configurable; Hardware

With advances in VLSI fabrication and chip placement and routing technology, the areaconsumed by a CPU and its traditional on-chip components has shrunk to the point of liberating significant chip area. Meanwhile, the use of reconfigurable logic such as Field-Programmable Gate Array (FPGA) devices is increasing, due to improvements in the speed and capacity of those devices. While commodity processors perform well for most applications, such processorscannot deliver the performance of a more customized approach. On the other hand, the cost of developing application-specific processors is quite expensive, and therefore not worthwhile unless many parts can be sold. Reconfigurable hardware offers an economical alternative to obtaining high performance, so that commodity processors of the future might enjoy increasingly greater levels of reconfigurability. This could bring customized logic within the reach of low-volume, high-performance applications. However, software and architectural innovations are required to make this happen. We propose to bring the advantages of custom logic to low-volume but high-performance applications by semiautomatically generating customized reconfigurable logic. By coupling soft-core commodity processors with reconfigurable logic, an application is essentially offered a liquid architecture, where the definitionand implementation of the computer's instruction set, its coprocessors' functionality, and its supporting structures can be easily changed. With proper software support, liquid architectures can improve the performance of many kinds of applications,ranging from high-performance, scientific calculations to low-power, embedded systems. Ourresearch aims to develop the software infrastructure and methodologies needed to obtain high performance of applications on reconfigurable hardware deployed in diverse settings.

随着 VLSI 制造以及芯片布局和布线技术的进步，CPU 及其传统片上组件所占用的面积已经缩小到可以释放大量芯片面积的程度。与此同时，由于现场可编程门阵列 (FPGA) 设备等可重构逻辑的速度和容量的提高，这些设备的使用正在增加。 虽然商用处理器对于大多数应用程序表现良好，但此类处理器无法提供更加定制的方法的性能。另一方面，开发专用处理器的成本相当昂贵，因此除非可以出售许多零件，否则不值得。 可重新配置的硬件为获得高性能提供了一种经济的替代方案，因此未来的商用处理器可能会享受越来越高水平的可重新配置性。这可以为小批量、高性能应用带来定制逻辑。然而，要实现这一目标，需要软件和架构创新。 我们建议通过半自动生成定制的可重构逻辑，将定制逻辑的优势引入小批量但高性能的应用程序。通过将软核商用处理器与可重构逻辑相结合，应用程序本质上提供了一种流动架构，其中计算机指令集的定义和实现、其协处理器的功能及其支持结构可以轻松更改。 通过适当的软件支持，液态架构可以提高多种应用的性能，从高性能科学计算到低功耗嵌入式系统。我们的研究旨在开发在不同环境中部署的可重构硬件上获得高性能应用程序所需的软件基础设施和方法。