ITR: Collaborative Research: A Multi-Level Approach to Power-Efficient Opto-Electronic Interconnection Networks

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Abstract:Interconnection network fabrics are becoming an ever-more critical communication backbone of many digital systems, providing the means for systems to scale up in capacity. As these systems become power-constrained, networks stand to be the weakest link, unless there is a shift from prior performance-driven approaches to one that focuses on the power efficiency of networks.This project takes a multi-level approach to power-efficient interconnection networks that synergistically bridges research in circuits, architecture and software, providing a complete solution that will make power-aware network fabrics a reality. Research into novel low-power circuit techniques develops basic network building blocks for newpower-efficient network architecture designs. New link and switch mechanisms uncovered at the circuit-level are leveraged for run-time architectural tradeoffs in network power and performance. Higher up in the hierarchy, the software level closest to users analyzes and factors in user power-performance requirements.This research targets a diverse range of systems -- (1) both general-purpose and embedded systems; (2) both electrical and optical networking technologies, seeking to determine the optimal choice between optical versus electrical interconnection at each level in the network hierarchy from a power perspective; (3) from tiny on-chip networks todata center-wide chassis-to-chassis networks.The research is integrated into the education curriculum, through existing and new graduate courses, and in undergraduate research programs. The project seeks to further broaden the participation of underrepresented groups in research activities. As a pioneering effort inpower-efficient interconnection networks, the project seeks tofacilitate future research and education in this area through the release of simulation tools and other results.