Flexible Voltage Stacking for Chip Multiprocessors

电源电压的有效管理对于克服未来高并行多核微处理器的功率限制至关重要。该项目提出了一种新的方法，通过一种称为柔性电压堆叠的技术，在芯片多处理器中有效地提供功率和管理电压。电压堆叠涉及向芯片提供更高的电源电压（导致固定功率预算的更低电流消耗），这可以减少IR损耗并提高功率传输效率。通过为堆栈提供灵活性，单个核心可以以这样一种方式堆叠，以便将电压调节到所需的核心电源水平。pi计划探索一系列架构和电路技术，以减轻与电压噪声相关的问题。此外，将设计一个原型芯片，演示灵活的电压堆栈概念，由多核系统的组合软件/FPGA模拟器的实际工作负载跟踪驱动。这项工作将通过技术转移到计算机行业，并为本科生和研究生提供培训，产生更广泛的影响。

Effective management of supply voltage is of critical importance to overcome power limitations in future highly parallel multi-core microprocessors. This project proposes a new approach to efficiently deliver power and manage voltage in chip multiprocessors through a technique, called flexible voltage stacking. Voltage stacking involves delivering a higher supply voltage to the chip (resulting in lower current draw for a fixed power budget), which can reduce IR losses and improve power delivery efficiency. By providing flexibility to the stack, individual cores can be stacked in such a way as to regulate the voltage to the desired core supply level. The PIs plan to explore a range of architectural and circuit techniques to mitigate issues related to voltage noise. Also, a prototype chip will be designed demonstrating the flexible voltage stack concept, driven by realistic workload traces from a combined software/FPGA simulator of a multicore system. The work will have broader impacts through technology transfer to the computing industry and by providing training for both undergraduate and graduate students.