ITR/NGS-Intelligent HW/SW Compilers for DSP Applications

ITR/NGS-用于 DSP 应用的智能硬件/软件编译器

• 批准号: 0325687
• 负责人: Jose Moura
• 金额: $ 140万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-09-01 至 2010-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0325687&HistoricalAwards=false
• 关键词: ITR; NGS; Intelligent; HW; SW

We propose to develop a system to automate the design, implementation, and optimization of digital signal processing (DSP) applications for software (SW), hardware (HW), and SW/HW platforms with respect to multiple, possibly conflicting, performance metrics including speed, accuracy, area, and power. Ours is a new system of intelligent design and optimization tools that incorporate domainspecific knowledge of the mathematical structure of DSP computations and use this knowledge for automatic optimization and exploration of the design space, controlled by search and feedback optimization techniques. By including the 'high' mathematical level into the design automation, we achieve the following two main goals. The project will (1) overcome the known limitations of current optimizing compilers and synthesis tools that do not have access to high level structural information and are thus restricted to mechanical source code level manipulations, and will provide the framework to conquer for automation that step in the design flow that has traditionally been reserved to human ingenuity: intelligent algorithm manipulation and implementation to optimize desired performance metrics under given constraints.

我们建议开发一个系统，以自动化的设计，实现和优化的数字信号处理（DSP）应用程序的软件（SW），硬件（HW），和SW/HW平台相对于多个，可能相互冲突，性能指标，包括速度，精度，面积和功率。我们的是一个新的系统的智能设计和优化工具，将domainspecific知识的DSP计算的数学结构，并使用此知识的自动优化和探索的设计空间，控制搜索和反馈优化技术。通过将“高”数学水平纳入设计自动化，我们实现了以下两个主要目标。该项目将（1）克服当前优化编译器和合成工具的已知限制，这些工具无法访问高级结构信息，因此仅限于机械源代码级别的操作，并将提供框架来征服设计流程中传统上保留给人类智慧的自动化步骤：智能算法操作和实现，以在给定的约束条件下优化所需的性能指标。