ITR: Architectures and Design Methodologies for Secure Low-Power Embedded Systems

嵌入式系统，例如信息设备和网络传感器，面临着一些最苛刻的安全问题——它们资源有限，同时经常需要在物理上不安全的环境中处理敏感信息。安全处理很容易压倒嵌入式处理器有限的计算和内存资源，特别是随着要处理的数据量的增加和高速网络的数据速率。这种“性能差距”由于“电池差距”而变得更加复杂，电池差距是指安全的低功耗嵌入式系统的能量需求和电池技术的缓慢进步之间的差距。该项目是对几项核心技术的跨学科研究，将使安全，低功耗嵌入式系统的设计成为可能。它涵盖了安全、加密算法、嵌入式处理器架构、计算机算法、低功耗设计以及使能设计方法和工具等领域。它解决了嵌入式处理器和系统的性能、能源和安全需求及其权衡。研究目标包括对嵌入式系统安全性的性能要求和功耗进行全面分析。该项目正在开发用于低功耗嵌入式系统安全处理的高效架构，包括用于片上系统设计的可配置安全模块，以及用于嵌入式系统的微型加密处理器的架构指南。研究了基于自定义协议、加密算法以及硬件和软件实现级别的性能、功耗和安全权衡。设计方法和工具包括处理器设计工具，以促进基于开放框架（如PLX（托管在普林斯顿大学）和SimpleScalar工具包）的新安全处理架构的设计。该项目探索领域特定的设计方法，这些方法联合设计安全协议和处理体系结构，以满足所需的安全、性能和功率优先级和约束。该研究使嵌入式系统的设计具有更高的安全性，同时与传统方法相比，在性能和电池寿命方面实现了数量级或更多。除了对未来的研究和教育产生影响外，还将对嵌入式系统设计产生广泛的安全影响。研究结果通过普林斯顿多媒体与安全架构实验室（PALMS）和NJCST嵌入式系统芯片设计中心传播给工业界。研究成果正在被纳入研究生和本科课程。

Embedded systems, for example in information appliances and networkedsensors, face some of the most demanding security concerns - they are resourceconstrained while frequently needing to handle sensitive information inphysically insecure environments. Security processing can easily overwhelm thelimited computation and memory resources of embedded processors, especially withthe escalation in the amount of data to be processed and the data rates ofhigh-speed networks. This "performance gap" is compounded by the "battery gap",which is the disparity between energy requirements and slow improvements inbattery technology, for secure low-power embedded systems. This project is an inter-disciplinary study of several core technologiesthat will enable the design of secure, low-power embedded systems. It spans thefields of security, cryptographic algorithms, embedded processor architecture,computer arithmetic, low power design, and enabling design methodologies andtools. It addresses the performance, energy and security requirements, andtheir tradeoffs, in embedded processors and systems. The research goals includea comprehensive analysis of the performance requirements and power consumptionfor security in embedded systems. The project is developing efficient architecturesfor security processing in low-power embedded systems, including configurablesecurity modules for system-on-chip designs, and architectural guidelines fortiny cryptographic processors for embedded systems. The performance, power andsecurity tradeoffs based on customizations at the protocol, cryptographicalgorithm, and hardware and software implementation levels are studied. Designmethodology and tools include processor design tools to facilitate the design ofnew security processing architectures based on open frameworks such as the PLX(hosted at Princeton) and SimpleScalar toolkits. The project exploresdomain-specific design methodologies that jointly co-design security protocolsand processing architectures to meet the required security, performance andpower priorities and constraints. The research enables the design of embedded systems with higher levels ofsecurity, while achieving an order of magnitude or more in performance andbattery life, compared to conventional approaches. Broad security impacts are expected for embedded system design, in addition to impact for future research and education. Results are disseminated to industry through the Princeton Architecture Lab for Multimedia and Security (PALMS) and the NJCST Center for Embedded System-on-a-Chip Design. The research results are being woven into graduate and undergraduate courses.