ITR: Architectures and Design Methodologies for Secure Low-Power Embedded Systems

嵌入式系统，例如信息设备和网络传感器，面临着一些最苛刻的安全问题-它们资源有限，同时经常需要在物理不安全的环境中处理敏感信息。嵌入式处理器有限的计算和内存资源很容易被安全处理所淹没，特别是随着要处理的数据量和高速网络的数据速率的增加。这种“性能差距”与“电池差距”相结合，电池差距是能源需求和电池技术缓慢改进之间的差距，用于安全的低功耗嵌入式系统。 该项目是一个跨学科的研究几个核心技术，将使安全，低功耗的嵌入式系统的设计。 它涵盖了安全、密码算法、嵌入式处理器体系结构、计算机算术、低功耗设计以及使能设计方法和工具等领域。 它解决了嵌入式处理器和系统的性能、能源和安全要求及其权衡。本文的研究目标是全面分析嵌入式系统的安全性能需求和功耗。该项目正在为低功耗嵌入式系统的安全处理开发高效的架构，包括用于片上系统设计的可配置安全模块，以及用于嵌入式系统的微型密码处理器的架构指南。 研究了基于协议、密码算法、硬件和软件实现层次定制的性能、功耗和安全权衡。 设计方法和工具包括处理器设计工具，以促进基于开放框架（如PLX（托管在普林斯顿）和SimpleScalar工具包）的新安全处理架构的设计。该项目探索特定领域的设计方法，共同设计安全协议和处理架构，以满足所需的安全性，性能和电源优先级和限制。 该研究使嵌入式系统的设计具有更高的安全级别，同时实现一个数量级或更多的性能和电池寿命，相比传统的方法。 除了对未来的研究和教育的影响外，预计嵌入式系统设计将产生广泛的安全影响。 研究结果通过普林斯顿多媒体和安全架构实验室（PALMS）和NJCST嵌入式系统芯片设计中心传播给业界。研究成果正被编入研究生和本科生课程。

Embedded systems, for example in information appliances and networkedsensors, face some of the most demanding security concerns - they are resourceconstrained while frequently needing to handle sensitive information inphysically insecure environments. Security processing can easily overwhelm thelimited computation and memory resources of embedded processors, especially withthe escalation in the amount of data to be processed and the data rates ofhigh-speed networks. This "performance gap" is compounded by the "battery gap",which is the disparity between energy requirements and slow improvements inbattery technology, for secure low-power embedded systems. This project is an inter-disciplinary study of several core technologiesthat will enable the design of secure, low-power embedded systems. It spans thefields of security, cryptographic algorithms, embedded processor architecture,computer arithmetic, low power design, and enabling design methodologies andtools. It addresses the performance, energy and security requirements, andtheir tradeoffs, in embedded processors and systems. The research goals includea comprehensive analysis of the performance requirements and power consumptionfor security in embedded systems. The project is developing efficient architecturesfor security processing in low-power embedded systems, including configurablesecurity modules for system-on-chip designs, and architectural guidelines fortiny cryptographic processors for embedded systems. The performance, power andsecurity tradeoffs based on customizations at the protocol, cryptographicalgorithm, and hardware and software implementation levels are studied. Designmethodology and tools include processor design tools to facilitate the design ofnew security processing architectures based on open frameworks such as the PLX(hosted at Princeton) and SimpleScalar toolkits. The project exploresdomain-specific design methodologies that jointly co-design security protocolsand processing architectures to meet the required security, performance andpower priorities and constraints. The research enables the design of embedded systems with higher levels ofsecurity, while achieving an order of magnitude or more in performance andbattery life, compared to conventional approaches. Broad security impacts are expected for embedded system design, in addition to impact for future research and education. Results are disseminated to industry through the Princeton Architecture Lab for Multimedia and Security (PALMS) and the NJCST Center for Embedded System-on-a-Chip Design. The research results are being woven into graduate and undergraduate courses.