CAREER: Design Automation of Integrated Power Electronics: From Architectures to Circuits

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Power management circuits and systems generally regulate voltage and current under battery drain, provide power conversion to various electronic loads for optimizing system efficiency, and provide low-noise supplies to sensitive circuits. At present, these systems are optimized through custom architecture selection and design optimization by an experienced team -- a process that is not conducive to the low-cost, fast-paced development cycles required for market deployment in consumer applications, e.g., IoT devices, wearables, and automotive. This project aims to develop a design flow that minimizes the number of complex steps requiring human oversight, substantially reduces product development cycle time and cost, and maximizes power-converter performance by considering performance variation/degradation over lifetime. The automation platform developed through this award will allow a small number of engineers to design and optimize these systems, enabling designers to spend more time on developing novel converter architectures and exploring the design space for new circuit topologies. The educational activities involve integrating design automation for integrated electronics with of student training from academic stages from K-12 through college level. The findings of the project will be incorporated into two courses at Arizona State University.This project will advocate a novel paradigm for automating design of analog systems, in particular power electronics. Integrated built-in-self-test will be used to monitor power system performance and update statistical models used during the design phase, thus increasing the occurrences of first-pass design success. The design automation of these closed-loop systems will be achieved through: a) creation of analytical models to express the numerous power converter architectures, b) development of a circuit component design library, c) a circuit simulation methodology for collecting a representative subset of design parameters that will correlate to the relevant performance space, d) creation of statistical models and data that can be used to fit to geometric programming (GP) and support vector machine (SVM) algorithms, and e) development of a computationally efficient and accurate optimization approach. The automation methods generated from this research effort, including the methodology for creating statistical models and collecting empirical data, the generated circuit component design library, and the algorithms for optimizing a closed-loop power converter system with hierarchical circuits may be used for design of other closed-loop or complex analog systems, such as phase-locked loops (PLLs) and sensors.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.