CAREER: Computer-Aided Design of Mixed ASIC / Reconfigurable Fabrics of the Nanometer Era

提案编号：0347891机构：明尼苏达州双城大学校长：Bazargan，KiaTitle：计算机辅助设计的混合ASIC /可重构结构的纳米时代摘要：芯片制造技术的改进带来了惊人的增长，电子系统，导致数千兆赫兹的时钟速度和十亿门芯片。然而，爆炸性的复杂性，不断上升的制造成本，缩短的上市时间窗口和深亚微米效应正在威胁着电子技术的持续增长。新的系统复杂性导致系统行为的不可靠性（甚至失败）和不可预测性。在SoC中采用类似FPGA（现场可编程门阵列）的可重构模块提高了灵活性并降低了非经常性工程（NRE）成本。嵌入式类似FPGA的可重构结构已经成为当今SoC的一部分，并且由于其提供的巨大优势，将不可避免地成为未来设计的一部分。 然而，在SoC中采用可重构结构的方式存在许多挑战性的障碍。该建议解决了许多这些挑战：1）提出了不同抽象级别的统计建模和优化，以考虑可靠性和可预测性问题。2)还研究了可重构织物的结构特征，以降低功耗并改善织物的热传导，同时优化灵活性，成本和性能。3)提出了混合ASIC /可重构结构的CAD算法，包括不确定性设计的分级评估和估计、低功耗优化和工艺映射，这些算法和方法将灵活性、可靠性和生产率作为一等公民进行优化，同时沿着其他设计质量指标，如面积、成本和性能。我们将把这项研究的一些结果在超大规模集成电路课程在明尼苏达大学，以及可重构计算的高级课程。此外，将开发一个网页，将托管所有课程材料，可重新配置的基准和FPGA工具，从我们的小组和其他研究人员。

PROPOSAL NO: 0347891INSTITUTION: U of Minnesota-Twin CitiesPRINCIPAL INVESTIGATOR: Bazargan, KiaTITLE: Computer-Aided Design of Mixed ASIC / Reconfigurable Fabrics of the Nanometer EraAbstract:Improvements in the chip manufacturing technology have brought about astonishing growth of electronic systems, resulting in multi-gigahertz clock speeds and billion-gate chips. However, explosive complexities, rising manufacturing costs, shrinking time-to-market windows, and deep submicron effects are threatening the continuation of the growth in the electronics technology. New system complexities result in unreliability (even failure) and unpredictability of system behavior. Employing FPGA-like (Field Programmable Gate Array) reconfigurable blocks in SoC promotes flexibility and drives non-recurring engineering (NRE) costs down.Embedded FPGA-like reconfigurable fabrics have emerged as part of todays SoC, and will inevitably be part of future designs because of the enormous advantages they provide. However, there are many challenging hurdles in way of employing reconfigurable fabrics within SoC. This proposal tackles a number of these challenges: 1) Statistical modeling and optimization at different levels of abstraction are proposed to take on the reliability and predictability concerns. 2) Architectural features for the reconfigurable fabrics are also investigated to reduce power and improve thermal conduction out of the fabric, while optimizing the flexibility, cost and performance. 3) CAD algorithms for mixed ASIC / reconfigurable fabric are proposed, and include hierarchical evaluation and estimation of uncertain designs, low power optimization and technology mapping.The proposed algorithms and methodologies would consider flexibility, reliability and productivity as first-class citizens to be optimized along with other design quality metrics such as area, cost, and performance. We will incorporate some of the results of this research in the VLSI courses at the University of Minnesota, as well as an advanced course on reconfigurable computing. Furthermore, a web page will be developed that would host all course material, reconfigurable benchmarks and FPGA tools from our group and other researchers.