U.S.-Japan Cooperative Science: Efficient Test and Diagnosis Techniques for System-on-Chip

该奖项支持北卡罗来纳州杜克大学的Krishnendu Chakrabarty教授和日本九州大学的Seji Kajihara教授之间为期两年的合作研究项目。他们将研究片上系统（SOC）的有效测试和诊断技术。VLSI技术的最新进展导致集成电路（ic）的密度迅速增加。密度的增加和对纳米技术中新型缺陷的测试需求导致测试数据量的巨大增加。测试数据量的增加不仅导致测试时间的增加，而且高测试数据量还可能超过自动测试设备（ATE）有限的内存深度。多次ATE重新加载非常耗时，因为从工作站到ATE硬盘或从ATE硬盘到ATE通道的数据传输非常慢。研究人员将研究几种新的方法来减少测试数据量和测试集成电路。这些技术基于数据压缩方法、备选扫描体系结构和内置自检（BIST）。从图像处理领域的压缩技术，如四叉树分解，将探讨。将开发一种扫描设计方法，其中将使用少量ATE通道来驱动多个扫描链。最后，将开发新的线性反馈移位寄存器（LFSR）重播架构，其中LFSR的种子可以通过指定触发器转移到LFSR中，该触发器可以从LFSR的一组预定触发器中选择。集成电路广泛应用于当今的电子系统中，应用范围从微处理器和消费电子产品到医疗和飞机控制系统等安全关键系统。为了确保这些系统的可靠运行，高质量的集成电路测试是必不可少的。为了降低产品成本，在不影响产品质量的前提下降低测试成本也是必要的。该项目有望为集成电路带来低成本的测试技术，从使用数据压缩的外部测试到BIST解决方案。这项研究最终将使SOC设计的集成度更高，并有助于弥合设计能力和制造能力之间的差距。这项研究的广泛影响将在缩短设计时间和提高各种电子产品的可靠性方面得到体现。该项目汇集了两个具有互补专业知识和研究能力的实验室的努力。通过思想和技术的交流，该项目将扩大我们的基础知识基础，促进国际了解与合作。该项目包括一名研究生的参与。研究结果将在科学会议和科学期刊上传播。

0403217ChakrabartyThis award supports a two-year collaborative research project between Professor Krishnendu Chakrabarty at Duke University in North Carolina and Professor Seji Kajihara at Kyushu University in Japan. They will be undertaking research on efficient test and diagnosis techniques for system-on-chip (SOC). Recent advances in VLSI technology have lead to a rapid increase in the density of integrated circuits (ICs). The increased density and the need to test for new types of defects in nanometer technologies result in a tremendous increase in test data volume. The increase in test data volume not only leads to the increase of testing time, but the high test data volume may also exceed the limited memory depth of automatic test equipment (ATE). Multiple ATE reloads are time-consuming since data transfer from a workstation to the ATE hard disk or from the ATE hard disk to ATE channels is very slow. The researchers will investigate several new approaches to reduce test data volume and testing for ICs. These techniques are based on data compression methods, alternative scan architectures, and built-in self-test (BIST). Compression techniques from the image-processing domain, such as quad tree decomposition, will be explored. A scan design approach will be developed in which a small number of ATE channels will be used to drive multiple scan chains. Finally, new linear-feedback shift-register (LFSR) reseeding architectures will be developed in which the seeds for the LFSR can be shifted into the LFSR through a designated flip-flop, which can be selected from a set of predetermined flip-flops of the LFSR. ICs are widely used in today's electronic systems, with applications ranging from microprocessors and consumer electronics to safety-critical systems such as medical and aircraft control systems. In order to ensure the reliable operation of these systems, high quality testing of ICs is essential. To reduce product cost, it is also necessary to reduce the cost of testing without compromising product quality in any way. This project is expected to lead to low-cost test techniques for ICs, ranging from external testing using data compression to BIST solutions. This research will eventually allow even higher levels of integration in SOC designs, and help bridge the gap between design capability and manufacturing capacity. The broad impact of this research will be seen in reduced design time and enhanced reliability of a wide range of electronic products.The project brings together the efforts of two laboratories that have complementary expertise and research capabilities. Through the exchange of ideas and technology, this project will broaden our base of basic knowledge and promote international understanding and cooperation. The project includes the participation of a graduate student. Results of the research will be disseminated at scientific meetings and in scientific journals.