Collaborative Research: New Directions for Advanced VLSI Manufacturability

题目：合作研究：先进VLSI可制造性的新方向摘要：随着VLSI技术的发展，设计体系不断缩小，复杂性不断增加，保持足够的验证、工艺窗口和制造良率变得越来越困难。该项目将研究布局设计和可制造性之间的几个新的关键问题，包括相移掩模的自动布局流，产量提高的区域填充合成，泄漏可变性控制的门长偏置，以及探索限制设计规则的原则方法。我们提出的研究的智力价值源于其对未来集成设计到制造流程的广泛概念化，以及对几个关键设计技术目标的选择性关注。这项工作将有助于缓解目前威胁摩尔定律和半导体技术路线图的一些挑战。

Proposal ID: 0429737PI/coPI: Gabriel Robins (UVA), Andrew Kahng (UCSD), Aleksandr Zelikovskiy (GA state)Title: Collaborative Research: New Directions for Advanced VLSI Manufacturability Abstract:As VLSI technology advances into ever shrinking design regimes and growing complexity, it is increasingly difficult to maintain adequate verification, process windows, and manufacturing yields. This project will investigate several newly critical issues at the interface between layout design and manufacturability, including automaticlayout flows for phase-shifting masks, area fill synthesis for yield improvement, gate-length biasing for leakage variability control, and principled methodologies for exploring restricted design rules. The Intellectual merit of our proposed research stems from its broad conceptualization of a future integrated design-to-manufacturing flow, coupled with its selective focus on several key design technology goals. This work will help alleviate some of the challenges that now threaten Moore's Law and the Semiconductor Technology Roadmap.