Research in Layout Optimization for Advanced Manufacturability Considerations

随着CMOS技术进入80纳米甚至更高的时代，制造工艺对物理版图设计和验证的影响越来越大。为了最大限度地提高产量，工艺工程师必须实现制造设备和互连属性的可预测性和一致性。该项目研究了版图设计和可制造性之间的新的关键问题，例如为了减少化学机械抛光的可变性而进行的版图修改，使用相移掩模和光学邻近校正的适合光学光刻的设计，以及其他问题。该项目正在开发强大的试验台、算法和工具来解决这些重要问题，并正在与行业合作伙伴互动，以量身定做拟议的方法，以解决实际测试用例和生产运行的实际目标。

As CMOS technology advances into the 80 nanometer generation and beyond, the manufacturing process is having an increasingly constraining effect on physical layout design and verification. To maximize yield, process engineers must achieve predictability and uniformity of manufactured device and interconnect attributes. This project investigates newly critical issues in the interface between layout design and manufacturability, such as layout modification for reduced variability of chemical-mechanical polishing, design which is amenable to optical lithography using phase-shifting masks and optical proximity correction, and other problems. This project is developing robust testbeds, algorithms and tools to address these important problems, and is interacting with industry partners to tailor the proposed approaches to address real objectives on actual test cases and production runs.