Research in Layout Optimization for Advanced Manufacturability Considerations

考虑先进可制造性的布局优化研究

• 批准号: 9988331
• 负责人: Gabriel Robins
• 金额: $ 42.19万
• 依托单位: University of Virginia Main Campus
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-08-15 至 2004-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9988331&HistoricalAwards=false
• 关键词: Research; Layout; Optimization; Advanced; Manufacturability

As CMOS technology advances into the 80 nanometer generation and beyond, the manufacturing process is having an increasingly constraining effect on physical layout design and verification. To maximize yield, process engineers must achieve predictability and uniformity of manufactured device and interconnect attributes. This project investigates newly critical issues in the interface between layout design and manufacturability, such as layout modification for reduced variability of chemical-mechanical polishing, design which is amenable to optical lithography using phase-shifting masks and optical proximity correction, and other problems. This project is developing robust testbeds, algorithms and tools to address these important problems, and is interacting with industry partners to tailor the proposed approaches to address real objectives on actual test cases and production runs.

随着CMOS技术发展到80纳米及更高一代，制造工艺对物理布局设计和验证的约束越来越大。 为了最大限度地提高成品率，工艺工程师必须实现制造的器件和互连属性的可预测性和一致性。 本项目研究了布局设计和可制造性之间的接口中的新的关键问题，例如用于减少化学机械抛光的可变性的布局修改，适用于使用相移掩模和光学邻近校正的光学光刻的设计，以及其他问题。 该项目正在开发强大的测试平台，算法和工具来解决这些重要问题，并与行业合作伙伴进行互动，以定制拟议的方法，以解决实际测试用例和生产运行中的真实的目标。