CSR---SMA:Single-Chip Heterogeneous Multiprocessor Systems: Defining a New Level of Design

在过去的25年中，已经出现了50亿美元的产业来开发和支持用于集成电路（IC）的合成、验证和分析的工具和语言。在未来五年内，集成电路设计将进一步改变，因为它将有可能在单个芯片上提供足够的晶体管，用于100个16位处理器。该系统将被设计为通过利用任务级并行来满足其性能目标。这些软件密集型系统将需要远远超出传统计算机辅助设计工具的建模能力。虽然软件工程技术也有助于设计辅助工具，但它们并没有解决性能的重要方面;这是设计真实的受限系统的关键目标。 这些系统的性能的核心是并发任务到并发处理元件上的调度。系统中某个点的瓶颈可能会导致系统范围的性能下降。本研究将探讨定义一个新的层次的单芯片异构多处理系统的设计建模。该项目将研究包括处理资源、应用程序任务和调度器在内的基础模型的开发，并将开发基于并发系统模型的诊断辅助工具和将在网站上提供的模拟器。这项研究将定义，演示和教授计算机系统建模的新水平。

A five billion dollar industry has arisen over the last 25 years to develop and support tools and languages for synthesis, verification, and analysis of integrated circuits (ICs). Within the next five years, IC design will further change as it will be possible to provide enough transistors on a single chip for on the order of a hundred 16-bit processors. The systems will be designed to meet their performance goals through the exploitation of task level parallelism. These software-intensive systems will require modeling capabilities far beyond traditional computer-aided design tools. While software engineering techniques also contribute as design aids, they do not address the important aspect of performance; a key goal in the design of real, constrained systems. Central to the performance of these systems is the scheduling of the concurrent tasks onto concurrent processing elements. Bottlenecks at one point in the system can cause system-wide performance degradations. This research will investigate defining a new level of modeling for the design of single-chip heterogeneous multiprocessing systems. The project will investigate the development of the underlying models that include processing resources, application tasks, and schedulers , and will develop a diagnostic aid based on the concurrent system model, and a simulator to be made available on a website. This research will define, demonstrate, and teach a new level of computer system modeling.