SBIR Phase I: Versatile Maskless Patterning Technology For Cost-Effective Fabrication of Microelectronic Packaging Products

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This Small Business Innovation Research (SBIR) research project aims to develop a multi-resolution large-area maskless lithography system and process flow for fabricating electronic packages, such as integrated circuit packages, multi-chip modules, and printed circuit boards. This technology will feature an SLM as a programmable mask, and multiple projection lenses that perform imaging over a wide magnification range. The variable magnification enables the pixel size in the image plane to be set, depending upon the feature size - for example, coarse features (e.g. 200-um-wide input / output pads) can be imaged using a much larger pixel size than that used to image fine features (e.g. 20-um-wide interconnecting traces). By selecting the optimum pixel size for a given type of feature, the patterning rate of the system can be optimized to achieve the highest throughput. This offers a significant improvement above other maskless lithography techniques, which are limited to imaging over small areas, and which operate at only a single magnification, and are therefore also limited in either the resolution or the throughput of the system. If successful the proposed maskless lithography system will enable cost-effective manufacturing of a variety of advanced microelectronic packaging modules that are required in low to medium volumes. It will reduce development and production costs of electronic components for applications that require low to medium volumes of a large number of different types of very-high-performance electronic modules, such as portable electronics, sensors, and a variety of communication and control circuits. Additionally, the multi-resolution patterning capability would be attractive for fabricating other devices that have feature sizes ranging from microns up to hundreds-of-microns on the same substrate, for example, MEMS, MOEMS, optoelectronic circuits, and microfluidics.