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The Ideal Nanowire Transistor-Materials Development for Contact-Doped ZnO Nanowires

接触掺杂 ZnO 纳米线的理想纳米线晶体管材料开发

基本信息

批准号：
172125987
负责人：
Dr. Hagen Klauk
金额：
--
依托单位：
Max-Planck-Institut für Festkörperforschung (MPI-FKF)
依托单位国家：
德国
项目类别：
Research Grants
财政年份：
2010
资助国家：
德国
起止时间：
2009-12-31 至 2014-12-31
项目状态：
已结题

来源：
https://gepris.dfg.de/gepris/projekt/172125987?language=en
关键词：
Ideal Nanowire Transistor Materials Development

项目摘要

ZnO nanowires with a diameter of about 20 to 100 nm are of interest for high-performance field-effect transistors (FETs) and integrated circuits for flexible electronics. Single-crystalline ZnO nanowires are readily prepared from solution, can be suspended in a variety of solvents to allow deposition and alignment on a variety of substrates, and have electron mobilities exceeding 20 cm2/Vs. For scaling purpose it is necessary to have a strategy for reducing the channel length of the devices. But the performance of ZnO nanowire FETs with short channel length is limited by the large contact resistance that results from the energy barrier at the interface between the ZnO and the metal contacts. Also, making nanowire FETs with short channels introduces the challenge of connecting small objects using high-throughput (i.e., low-resolution) patterning techniques. We propose to solve these challenges by creating ZnO nanowires with self-aligned, selectively doped contacts. We will demonstrate the operation of these “ideal” n-i-n nanowires by making FETs and circuits on a single ZnO nanowire using an ultra-thin gate dielectric based on a self-assembled monolayer. The total length of the nanowires will exceed 10 μm, making them accessible by conventional photolithography or printing. Owing to the doped contact regions, the contact resistance will be greatly reduced. And by adjusting the length of the intrinsic region at the center of the nanowires we will obtain FETs with a channel length of less than 100 nm.

直径约为20至100 nm的ZnO纳米线对于高性能场效应晶体管（FET）和柔性电子器件的集成电路是有意义的。单晶ZnO纳米线很容易从溶液中制备，可以悬浮在各种溶剂中，以允许在各种衬底上沉积和对准，并且具有超过20 cm 2/Vs的电子迁移率。为了缩放的目的，有必要有一个策略，用于减少器件的沟道长度。但是，由于ZnO与金属接触界面处的能垒导致的大接触电阻限制了短沟道长度ZnO纳米线FET的性能。此外，制造具有短沟道的纳米线FET引入了使用高吞吐量（即，低分辨率）图案化技术。我们建议解决这些挑战，通过创建ZnO纳米线与自对准，选择性掺杂接触。我们将展示这些“理想”的n-i-n纳米线的操作，通过使用基于自组装单层的超薄栅极电介质在单个ZnO纳米线上制作FET和电路。纳米线的总长度将超过10 μm，使得它们可以通过传统的光刻或印刷来实现。由于掺杂的接触区，接触电阻将大大降低。通过调节纳米线中心本征区的长度，我们将获得沟道长度小于100 nm的FET。