CAREER: Streamlining Data Communication in Network Servers

互联网的发展导致了用于网络内容、流媒体和网络存储等服务的网络服务器的快速发展。网络服务器以多种不同的形式向最终用户提供数据。因此，它们的输入/输出(I/O)单元对性能至关重要。然而，主机CPU和I/O之间的通信接口存在瓶颈，这导致硬件和软件级别的效率低下。这项研究的目标是改进这些通信接口，使服务器性能能够随着每秒10千兆位以上的网络链路而扩展。该方法利用网络处理器和可编程网络接口来简化网络服务器中的数据通信。虽然现代主机CPU已经利用指令级并行(ILP)和数据缓存来提高性能，但诸如TCP/IP联网之类的任务并不是很适合这些技术。相比之下，TCP/IP的流数据和连接级并发性自然地映射到网络处理器的无缓存、多线程和多处理器核心，从而促使将高性能的TCP/IP网络堆栈卸载到这些设备。主机CPU和网络接口之间的协作计算和存储还允许在网络接收上避免复制，并通过将TCP协议处理从主机卸载到网络接口来减少代价高昂的中断。在此研究期间开发的新工作负载还推动了主机处理器和网络处理器的系统级架构增强。通过此研究产生的所有软件和工具都将通过开源分发转移到社区。这项研究的成果正被引入到针对大一和大二学生的课程中，以介绍计算机工程中的系统级概念，从BIT和晶体管等基础知识开始，最终发展到微体系结构和系统主题。

The growth of the Internet has led to rapid developments in network servers for services such as web content, streaming media, and networked storage. Network servers provide data in many different forms to end-users. Thus their input/output (I/O) units are critical to performance. However, there is a bottleneck in the communication interfaces between the host CPU and the I/O. This causes inefficiencies at both the hardware and software levels. The goal of this research is to improve these communication interfaces to allow server performance to scale with network links of 10 Gigabits per second and beyond.This approach utilizes network processors and programmable network interfaces to streamline data communication in network servers. While modern host CPUs have exploited instruction-level parallelism (ILP) and data caches to improve performance, tasks such as TCP/IP networking are not known to be well suited to these techniques. In contrast, the streaming data and connection-level concurrency of TCP/IP maps naturally to the cacheless, multithreaded and multiprocessor cores of network processors, motivating the offloading of a high-performance TCP/IP network stack to such devices. Cooperative computation and storage between the host CPU and the network interface also allows for copy-avoidance on network receive and for reducing costly interrupts by offloading TCP protocol processing from the host to the network interface. The new workloads developed during this research also motivate system-level architectural enhancements for both the host processor and the network processor.All software and tools produced through this research will be transferred to the community through open-source distribution. The results of the research are being introduced into courses targeted at freshmen and sophomores to introduce systems-level concepts in computer engineering starting from basics such as bits and transistors and culminating in micro-architecture and systems topics.