CSR: Small: Statistical Memory Monitoring in Hardware for Security and Performance

点击翻译按钮获取中文摘要

This project applies statistical sampling techniques to detect deviation from normal or desired behavior for a variety of applications, ranging from security problems such as phase-change memory (PCM) wear leveling and intrusion detection to performance problems such as multicore communication, data migration, and locality optimizations. Existing performance monitoring and measurement techniques are insufficient for our applications for a variety of reasons. Many depend upon the OS which (1) may be compromised and hence be unsuitable for security-related monitoring, and (2) tracks data at page granularity whereas memory hierarchy performance often needs monitoring at the block granularity. To avoid these limitations, this project designs a monitoring architecture for statistically sampling memory access patterns. Brute-force monitoring would require large, frequently-searched hardware structures that increase complexity and power, whereas sampling enables much smaller structures that are searched at low rates, incurring far less overhead. In general, sampling loses accuracy or requires a large number of samples (and large hardware structures) if the monitored behavior exhibits high standard deviation. Our key insight is that we can bound the standard deviation of the behavior within the region of interest to the application, thereby allowing accurate and low-overhead sampling. Our key intellectual merit is to show that statistical sampling and performance monitoring can unify the aims of disparate applications and enable monitoring with high accuracy and low overhead. The broader impacts include paving the way for robust statistics-based performance monitoring in future computer systems and for research and education efforts that combine statistics and computer architecture.