CRI: IAD: Accelerator-Based High-Performance Computing

商用处理器是高度可编程的，但它们需要支持通用计算，这限制了峰值和持续性能。这种观察促使使用“加速器”板，其是通过标准硬件总线（诸如PCI-Express）与主机服务器接口的协处理元件，但具有它们自己的计算引擎，并且通常也具有它们自己的存储器。与主处理器不同，加速器不支持一般应用程序;相反，它的硬件和软件只针对特定类型的计算进行调整。 加速器可以从主机处理器卸载应用程序中要求最高的部分，从而使用其专用资源加速所需的计算。这种性能的提高使各种形式的高性能计算（HPC）成为可能，但在可编程性方面付出了高昂的代价。本研究的目标是使用基于PC的集群进行高性能计算研究，以提高成本和可扩展性，并结合加速器实现高性能。Purdue珠峰项目包括几个相关的努力，以实现高性能、低功耗和高度异构系统的高可编程性。 获得一个30节点的基于千兆以太网的多核基于PC的工作站集群，这些工作站配备有各种加速器板（例如，GPU，Cell，FPGA，Crypto）将使研究能够有效和高度可编程地使用基于加速器的集群。每个节点支持多个加速器允许应用程序在不同阶段使用不同的加速器板。 该集群还允许通过保持其他系统因素不变来公平地比较不同的加速器。本研究还调查了多个并发域的使用，跨集群的并行性，在一个单一的节点中的核心，在一个单一的节点中的主机处理器和加速器，并在一个给定的加速器的处理元素。

Commodity processors are highly programmable, but their need to support general purpose computation limits both peak and sustained performance. Such observations have motivated the use of "accelerator" boards, which are co-processing elements that interface with the host server through a standard hardware bus such as PCI-Express but have their own computational engine and typically their own memory as well. Unlike the main processor, the accelerator does not support general applications; instead, its hardware and software is tuned for only specific types of computations. Accelerators can offload the most demanding parts of an application from the host processor, speeding up the desired computation using their specialized resources. This improved performance enables various forms of high-performance computing (HPC), but comes at a high cost in programmability.This research targets high-performance computing research using PC-based clusters for cost and scalability combined with accelerators for high performance. The Purdue Everest project encompasses several related efforts in achieving high performance, low power consumption, and high programmability for highly heterogeneous systems. Acquiring a 30-node Gigabit Ethernet-based cluster of multicore PC-based workstations equipped with various accelerator boards (e.g., GPU, Cell, FPGA, Crypto) will enable research into effective and highly-programmable use of accelerator-based clusters. Supporting multiple accelerators per node allows applications to use different accelerator boards in different phases. This cluster also allows fair apples-to-apples comparisons of different accelerators by keeping the other system factors constant. This research also investigates the use of multiple concurrency domains, with parallelism across the cluster, across the cores in a single node, among the host processors and accelerators in a single node, and across the processing elements of a given accelerator.