Design Methodologies for Defect-Tolerant Computing Systems

CCF-0541169 PI：贝塔科，瓦莱里亚研究所：密歇根大学安娜堡分校标题：容错计算系统的设计方法该提案的重点是开发能够容忍硅硬件中中等数量缺陷的计算系统。对于硬件部件来说，硅缺陷是一个紧迫的问题，主要是因为晶体管的尺寸缩小到几十纳米。该提案从几个角度攻击了这一目标：首先，它开发了一个框架，用于分析与一系列硅故障相关的影响和暴露风险。在这种背景下，分析的故障类型是：1)软错误，即由于大气中存在的能量粒子而导致的瞬时故障，估计这些故障将在未来几年与硅技术相关；2)由于制造小型晶体管部件的不精确而导致的制造缺陷；以及3)磨损故障，由于晶体管在接近纳米尺寸时变弱。该提案的第二个目标是开发软件，以支持对一系列潜在的未来情景的分析和评估，其中包括这些类型的故障。最后，该建议的第三个目标是开发两个实验性微处理器设计，它们探索弹性系统设计空间中的两个解决方案：一个设计可以承受中到高度的缺陷，而另一个设计只能承受第一次故障，但对成本和性能的影响最小。

CCF-0541169 PI: Bertacco, Valeria Institution: University of Michigan Ann Arbor Title: Design Methodologies for Defect-Tolerant Computing Systems The proposal focuses on the development of computing systems capable of tolerating a moderate to medium number of defects in the silicon hardware. Silicon defects are a pressing problem for hardware parts, mainly because of the shrinking of transistors sizes down to a few tens of nanometers. The proposal attacks this goal from a few angles: first it develops a framework for the analysis of the impact and exposure risks associated with a range of silicon failures. In this context, the types of failures analyzed are: 1) soft-errors, that is, transient faults due to energy particles present in the atmosphere, which are estimated to be relevant for silicon technologies in the next few years; 2) manufacturing defects due to the imprecision of manufacturing small scale transistor parts; and 3) wear-out failures, due to the weakening of transistors as they approach nanometer sizes. The second goal of the proposal develops software to support the analysis and evaluation of a range of potential future scenarios, which include these types of failures. Finally, the third goal of this proposal develops two experimental microprocessor designs which explore two solutions points in the resilient systems design space: one design can sustain a medium to high level of defects, while the other can sustain only the first failure but with a minimum cost and performance impacts.