Error Correction Systems for Nano-Scale Fault-Tolerant Memories

在这项拟议的研究中，将开发由不可靠组件制成的高度可靠的存储器，并根据其复杂性和保存存储信息的能力进行表征。主要的挑战是，在纳米级系统中，存储元件和逻辑门都有故障。与现有系统相比，只有存储元件被认为是不可靠的，而纠错编码器和解码器被假设由可靠的逻辑门组成。本研究将解决的一组问题可以归结为以下问题：给定n个存储单元和m个通用逻辑门，它们遵循已知的随机机制失效，在任意低错误概率的情况下，在最长的时间段内存储最大数量的信息比特的最佳存储结构是什么？这个复杂的问题可以用许多方式来划分和重新表述，但有趣的是，即使是与这个问题有关的一些最根本的问题也仍然没有答案。最重要的问题涉及容错存储器中的以下两种根本不同的方法：(I)为了提高可靠性，可以将逻辑门资源投资到冯·诺伊曼多路复用方案中。通过这种方式，可以构建高度冗余的可靠网络，模拟通用逻辑门的功能，然后使用这种更好的门来构建纠错编解码器。(Ii)可替换地，可以将逻辑门资源投资于构建能够处理存储元件以及逻辑门错误的更强大的纠错码(即，解码器)。对于给定的故障机制，这两种方法中哪一种是最优的？从更广泛的范围来看，是在设备上还是在系统层面上处理可靠性问题更好？智能优点：纳米系统的独特特性--存储元件和逻辑门都不可靠--使得确保容错的问题在理论上非常重要，因为纠错过程并不像经典信息论中假设的那样是无错误的。使纠错码更强大，使发射机和接收机更复杂，并不一定会改善系统的性能。对于给定的故障机制，可能存在接收器复杂性和性能之间的权衡。我们开发容错存储体系结构的方法基于Taylor开发的方法，并由Kuznetsov改进。Taylor和Kuznetsov(TK)证明了存储系统具有非零计算(存储)能力，即确保可靠性所需的冗余度随着存储容量的增加而渐近线性增长。这项研究将解决两个基本的开放问题：确定纳米级存储器的存储容量和开发接近容错结构的容量。TK方法中的恢复阶段和错误的Gallager-B算法(如项目说明中所述)的等价性，将使我们能够利用过去十年中在图形代码和迭代解码中获得的大量知识，在不可靠的介质上解决这些和其他重要的存储问题。广泛影响：该计划将对美国和国外的数据存储技术和信息基础设施的发展做出重大贡献。另一个重要方面是将编码和信号处理方面的知识以及纳米级设备和子系统整合到亚利桑那大学的本科生和研究生以及工业技术研究界的项目中。

In the proposed research, highly reliable memories made of unreliable components will be developedand characterized in terms of their complexity and ability to retain the stored information. The main challenge is that in nano-scale systems both the storage elements and logic gates are faulty. It is in contrast to the state-ofthe- art systems where only the memory elements are considered unreliable while error correction encoders and decoders are assumed to be made of reliable logic gates.The set of problems that will be addressed in this research can be condensed into the following question:given n memory cells and m universal logic gates which fail following a known random mechanism, what is the optimal memory architecture which stores the maximum number of information bits for the longest period of time with arbitrary low probability of error? This complex problem can be divided and reformulated in many ways, but, interestingly, even some of the most fundamental questions related to this problem are still unanswered. The most important question is related to the following two fundamentally different approaches in fault-tolerant memories: (i) To improve reliability, the logic gate resources may be invested into a von Neumann multiplexing scheme. In this way, one can build highly redundant reliable networks that simulate the function of universal logic gates, and then use such better gates to build an error correction encoder and decoder. (ii)Alternatively, the logic gate resources may be invested into building a more powerful error correcting code (i.e.,decoder) capable of handling both memory elements as well as logic gates errors. Which of these twoapproaches is optimal for a given failure mechanism? On a broad scale, is it better to deal with a reliability issue on a device or on a system level?Intellectual Merit:The unique feature of the nano-systems that both the storage elements and logic gates are unreliable makes the problem of ensuring fault-tolerance theoretically very important, because the process of error correction is not error-free as assumed in classical information theory. Making error correcting codes stronger and transmitters and receivers more complex will not necessarily improve the performance of a system. It is likely that for a given failure mechanism, there is a trade off between receiver complexity and its performance.Our approach to developing fault-tolerant memory architectures is based on a method developed byTaylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzerocomputational (storage) capacity, i.e. the redundancy necessary to ensure reliability grows asymptoticallylinearly with the memory size. Two fundamental open problems that will be addressed in this research aredetermining storage capacity of nano-scale memories and the development of capacity approaching fault-tolerant architectures. The equivalence of the restoration phase in the TK method and faulty Gallager-B algorithm (as explained in Project Description), will enable us to tackle these and other important problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade.Broader Impact:This program will contribute significantly to the evolution of data storage technologies and the informationinfrastructure in the United States of America and abroad. Another important aspect is the establishment of atight interdisciplinary integration of knowledge in coding and signal processing, and nano-scale devices andsubsystems into programs benefiting undergraduate and graduate students at the University of Arizona and theindustrial technical research community.