Error Correction Systems for Nano-Scale Fault-Tolerant Memories

纳米级容错存储器的纠错系统

• 批准号: 0634969
• 负责人: Bane Vasic
• 金额: $ 30万
• 依托单位: University of Arizona
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-10-01 至 2010-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0634969&HistoricalAwards=false
• 关键词: Error; Correction; Systems; Nano; Scale

In the proposed research, highly reliable memories made of unreliable components will be developedand characterized in terms of their complexity and ability to retain the stored information. The main challenge is that in nano-scale systems both the storage elements and logic gates are faulty. It is in contrast to the state-ofthe- art systems where only the memory elements are considered unreliable while error correction encoders and decoders are assumed to be made of reliable logic gates.The set of problems that will be addressed in this research can be condensed into the following question:given n memory cells and m universal logic gates which fail following a known random mechanism, what is the optimal memory architecture which stores the maximum number of information bits for the longest period of time with arbitrary low probability of error? This complex problem can be divided and reformulated in many ways, but, interestingly, even some of the most fundamental questions related to this problem are still unanswered. The most important question is related to the following two fundamentally different approaches in fault-tolerant memories: (i) To improve reliability, the logic gate resources may be invested into a von Neumann multiplexing scheme. In this way, one can build highly redundant reliable networks that simulate the function of universal logic gates, and then use such better gates to build an error correction encoder and decoder. (ii)Alternatively, the logic gate resources may be invested into building a more powerful error correcting code (i.e.,decoder) capable of handling both memory elements as well as logic gates errors. Which of these twoapproaches is optimal for a given failure mechanism? On a broad scale, is it better to deal with a reliability issue on a device or on a system level?Intellectual Merit:The unique feature of the nano-systems that both the storage elements and logic gates are unreliable makes the problem of ensuring fault-tolerance theoretically very important, because the process of error correction is not error-free as assumed in classical information theory. Making error correcting codes stronger and transmitters and receivers more complex will not necessarily improve the performance of a system. It is likely that for a given failure mechanism, there is a trade off between receiver complexity and its performance.Our approach to developing fault-tolerant memory architectures is based on a method developed byTaylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzerocomputational (storage) capacity, i.e. the redundancy necessary to ensure reliability grows asymptoticallylinearly with the memory size. Two fundamental open problems that will be addressed in this research aredetermining storage capacity of nano-scale memories and the development of capacity approaching fault-tolerant architectures. The equivalence of the restoration phase in the TK method and faulty Gallager-B algorithm (as explained in Project Description), will enable us to tackle these and other important problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade.Broader Impact:This program will contribute significantly to the evolution of data storage technologies and the informationinfrastructure in the United States of America and abroad. Another important aspect is the establishment of atight interdisciplinary integration of knowledge in coding and signal processing, and nano-scale devices andsubsystems into programs benefiting undergraduate and graduate students at the University of Arizona and theindustrial technical research community.

在拟议的研究中，将开发由不可靠组件组成的高度可靠的存储器，并根据其复杂性和保留存储信息的能力对其进行表征。主要的挑战是，在纳米级系统中，存储元件和逻辑门都有故障。这与只有存储器元件被认为是不可靠的，而纠错编码器和解码器被认为是由可靠的逻辑门组成的最先进的系统相反。在这项研究中将要解决的一系列问题可以浓缩为以下问题：给定N个存储单元和M个通用逻辑门按照已知的随机机制失效，什么是最佳的存储器结构，它在最长的时间内存储最大数量的信息位，并且具有任意低的概率，错误？这个复杂的问题可以以多种方式划分和重新表述，但有趣的是，即使是与这个问题有关的一些最基本的问题仍然没有答案。最重要的问题涉及容错存储器中的以下两种根本不同的方法：（i）为了提高可靠性，逻辑门资源可以被投入到冯诺依曼多路复用方案中。通过这种方式，人们可以构建高度冗余的可靠网络，模拟通用逻辑门的功能，然后使用这种更好的门来构建纠错编码器和解码器。（ii）可替换地，逻辑门资源可以被投资于构建更强大的纠错码（即，解码器）能够处理存储器元件以及逻辑门错误。对于给定的失效机制，这两种方法中哪一种是最佳的？在广泛的范围内，在设备或系统级别上处理可靠性问题更好？智力优点：纳米系统的独特之处在于存储元件和逻辑门都不可靠，这使得确保容错性的问题在理论上非常重要，因为纠错过程并不像经典信息论中假设的那样是无错误的。使纠错码更强，发射机和接收机更复杂，并不一定会提高系统的性能。很可能，对于一个给定的故障机制，有接收器的复杂性和它的performance.Our方法之间的权衡开发容错存储器架构是基于一种方法开发的泰勒和完善的库兹涅佐夫。Taylor和Kuznetsov（TK）证明了存储系统具有非零的计算（存储）容量，即确保可靠性所需的冗余度随着存储器大小渐近线性地增长。本研究将解决两个基本的开放问题：确定纳米级存储器的存储容量和发展接近容错架构的容量。在TK方法和错误的Gallager-B算法（如项目说明中所解释的）的恢复阶段的等效性，将使我们能够解决这些和其他重要问题，在可靠的存储不可靠的媒体上使用的大量知识在代码的图形和迭代解码在过去十年中获得。更广泛的影响：该计划将大大有助于数据存储技术的发展和informationinfrastructure在美国和国外。另一个重要方面是建立了编码和信号处理知识的跨学科整合，以及纳米级器件和子系统到亚利桑那大学和工业技术研究社区的本科生和研究生受益的计划。