CAREER: Semantics and Hardware Implementation of Transactional Memory

职业：事务内存的语义和硬件实现

• 批准号: 0644197
• 负责人: Milo Martin
• 金额: $ 32万
• 依托单位: University of Pennsylvania
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-06-01 至 2013-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0644197&HistoricalAwards=false
• 关键词: CAREER; Semantics; Hardware; Implementation; Transactional

After decades of research on shared-memory multiprocessors, computers with multiple processors have now been widely embraced with the arrival of the multicore revolution. Unlike the previous microprocessor revolution---which required no fundamental software changes---the multicore revolution requires a significant shift for software. Because much of the accustomed exponential performance improvements over the next decade will come directly from multiplying the number of processor cores on a chip, programmers that wish to harness this computational power must undertake the difficult task of creating parallel versions of their programs.To reduce the difficulty of this task of creating correct and efficient shared-memory programs, recent work on "transactional memory" has focused on providing the programmer with a higher-level primitive than just lock- based critical sections for managing concurrency in their shared-memory programs: a region of code annotated to execute as if it was not running in parallel with other code. Although conceptually serial, advanced implementations allow for concurrent execution while still providing a serializable semantics.The goal of this research is to identify, understand, and resolve the most important semantic and implementation challenges of hardware-based transactional memory. Just as the multiprocessor research successfully overcame important challenges, this research tackles the analogous challenges for hardware transactional memory: (i) understanding the semantics of the hardware/software interface, (ii) developing simple and fast hardware implementations, and (iii) creating critical experimental simulation and workload infrastructures.

经过几十年对共享内存多处理器的研究，随着多核革命的到来，具有多个处理器的计算机现在已经被广泛接受。 不像以前的微处理器革命-不需要基本的软件变化-多核革命需要软件的重大转变。 由于未来十年习惯的指数级性能改进将直接来自芯片上处理器核心数量的增加，因此希望利用这种计算能力的程序员必须承担创建程序并行版本的艰巨任务。为了降低创建正确且高效的共享内存程序这一任务的难度，最近关于“事务存储器”的工作集中于向程序员提供比仅仅基于锁的临界区更高级的原语，用于管理他们的共享存储器程序中的并发性：注释为执行的代码区域，就好像它没有与其他代码并行运行一样。 虽然在概念上串行，先进的实现允许并发执行，同时仍然提供了一个serializable semantic.The研究的目标是识别，理解，并解决最重要的语义和基于硬件的事务存储器实现的挑战。 正如多处理器研究成功地克服了重要的挑战，这项研究解决了硬件事务存储器的类似挑战：（i）理解硬件/软件接口的语义，（ii）开发简单快速的硬件实现，（iii）创建关键的实验模拟和工作负载基础设施。